Multi-functional transistors in semiconductor devices

Patent metadata

Field	Value
Publication number	US-2022406666-A1
Application number	US-202217738948-A
Country	US
Kind code	A1
Filing date	May 6, 2022
Priority date	Jun 18, 2021
Publication date	Dec 22, 2022
Grant date	—

Abstract

A semiconductor device with different gate structures and a method of fabricating the same are disclosed. The a method includes forming a fin structure on a substrate, forming a thermal oxide layer on top and side surfaces of the fin structure, forming a polysilicon structure on the thermal oxide layer, doping portions of the fin structure uncovered by the polysilicon structure to form doped fin portions, forming a nitride layer on the polysilicon structure and the thermal oxide layer, forming an oxide layer on the nitride layer, doping the nitride layer with halogen ions, forming a source/drain region in the fin structure and adjacent to the polysilicon structure, and replacing the polysilicon structure with a gate structure.

First claim

What is claimed is:

1 . A method, comprising:
forming a fin structure on a substrate; forming a thermal oxide layer on top and side surfaces of the fin structure; forming a polysilicon structure on the thermal oxide layer; doping portions of the fin structure uncovered by the polysilicon structure to form doped fin portions; forming a nitride layer on the polysilicon structure and the thermal oxide layer; forming an oxide layer on the nitride layer; doping the nitride layer with halogen ions; forming a source/drain region in the fin structure and adjacent to the polysilicon structure; and replacing the polysilicon structure with a gate structure.

2 . The method of claim 1 , wherein forming the thermal oxide layer comprises performing a thermal oxidation process on the fin structure.

3 . The method of claim 1 , wherein doping the portions of the fin structure comprises performing an ion implantation on the fin structure through the thermal oxide layer.

4 . The method of claim 1 , wherein doping the portions of the fin structure comprises doping the portions of the fin structure with a dopant concentration less than a dopant concentration of the source/drain region.

5 . The method of claim 1 , wherein doping the nitride layer with the halogen ions comprises performing an ion implantation with fluorine ions on the nitride layer.

6 . The method of claim 1 , wherein doping the nitride layer with the halogen ions comprises performing an ion implantation with fluorine ions at an implantation energy of about 20 KeV to about 30 KeV.

7 . The method of claim 1 , further comprising performing an anneal process on the nitride layer after doping the nitride layer with the halogen ions.

8 . The method of claim 1 , wherein forming the source/drain region in the fin structure comprises:
epitaxially growing a semiconductor material on the fin structure; and doping the semiconductor material with a dopant concentration greater than a dopant concentration of the doped fin portions.

9 . The method of claim 1 , further comprising etching portions of the oxide layer and the nitride layer that are not on sidewalls of the polysilicon structure.

10 . The method of claim 9 , further comprising etching portions of the thermal oxide layer exposed after etching the portions of the nitride layer.

11 . A method, comprising:
forming a first fin structure with a first fin width and a second fin structure with a second fin width on a substrate, wherein the second fin width is greater than the first fin width; forming first and second thermal oxide layers on the first and second fin structure, respectively; forming first and second polysilicon structures on the first and second thermal oxide layers, respectively; forming a masking layer on the first polysilicon structure and the first thermal oxide layer; doping portions of the second fin structure uncovered by the second polysilicon structure to form doped fin portions; forming a nitride layer on the first and second polysilicon structures and the first and second thermal oxide layers; forming an oxide layer on portions of the nitride layer on the second polysilicon structure and the second thermal oxide layer; doping the portions of the nitride layer on the second polysilicon structure and the second thermal oxide layer with halogen ions; and replacing the first and second polysilicon structures with first and second gate structures.

12 . The method of claim 11 , wherein doping the portions of the nitride layer comprises performing an ion implantation with fluorine ions on the portions of the nitride layer.

13 . The method of claim 11 , wherein doping the portions of the nitride layer comprises performing an ion implantation with fluorine ions at an implantation energy of about 20 KeV to about 30 KeV.

14 . The method of claim 11 , further comprising etching portions of the oxide layer and the nitride layer that are not on sidewalls of the first and second polysilicon structures.

15 . The method of claim 11 , wherein replacing the first and second polysilicon structures with the first and second gate structures comprises:
etching the first and second polysilicon structures; forming a masking a layer on a portion of the second thermal oxide layer exposed after etching the second polysilicon structure; and etching a portion of the first thermal oxide layer exposed after etching the first polysilicon structure.

16 . The method of claim 11 , wherein replacing the first and second polysilicon structures with the first and second gate structures comprises:
forming a first non-thermal oxide layer in physical contact with the first fin structure; and forming a second non-thermal oxide layer in physical contact with the second thermal oxide layer.

17 . A semiconductor device, comprising:
a substrate; a fin structure disposed on the substrate; a gate structure disposed on the fin structure; a gate spacer with a nitride layer and an oxide layer disposed on a sidewall of the gate structure, wherein a gate oxide layer of the gate structure extends under the gate spacer; a first source/drain region disposed in a portion of the fin structure under the gate spacer, wherein a width of the first source/drain region is substantially equal to a width of the gate spacer; and a second source/drain region disposed adjacent to the first source/drain region and on the fin structure.

18 . The semiconductor device of claim 17 , wherein the nitride layer comprises fluorine dopants.

19 . The semiconductor device of claim 17 , wherein a dopant concentration of the second source/drain region is greater than a dopant concentration of the first source/drain region.

20 . The semiconductor device of claim 17 , wherein a ratio between a thickness of the nitride layer and a thickness of the oxide layer is about 1:1 to about 1:3.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Cheng-Chieh
• Chiang Chen-Chieh
• Lin Wen-Sheng
• Chang Hsun-Jui
• Chen Yen-Han

Classifications

• H01L21/823871

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic

• H01L21/823864 Primary

  Electricity · mapped topic

• H01L29/401

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic