Image sensor including counter performing shifting operation and operation method thereof

Patent metadata

Field	Value
Publication number	US-12477249-B2
Application number	US-202318371167-A
Country	US
Kind code	B2
Filing date	Sep 21, 2023
Priority date	Feb 24, 2023
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

Disclosed is a counter which generates a binary code and a digital signal The counter includes: a reset memory circuit configured to store a sum of N reset binary codes, each of the N reset binary codes corresponding to a result of comparing a reset signal of the pixel signal with the ramp signal, and to calculate one of the N reset binary codes by performing a shifting operation on the sum of the N reset binary codes; and an output memory circuit configured to output the digital signal based on the N reset binary codes, a first image binary code indicating a result of comparing a first image signal of the pixel signal with the ramp signal once, and N sum binary codes, the N sum binary codes respectively indicating N results of comparing a sum signal of the pixel signal with the ramp signal.

First claim

What is claimed is:

1 . A counter which generates a binary code corresponding to a result of comparing a pixel signal output from a plurality of pixel groups of a pixel array with a ramp signal and generates a digital signal corresponding to the pixel signal based on the binary code, the counter comprising:
a reset memory circuit configured to store a sum of N reset binary codes, each of the N reset binary codes corresponding to a result of comparing a reset signal of the pixel signal with the ramp signal, and to calculate one of the N reset binary codes by performing a shifting operation on the sum of the N reset binary codes; and an output memory circuit configured to output the digital signal based on the N reset binary codes, a first image binary code indicating a result of comparing a first image signal of the pixel signal with the ramp signal once, and N sum binary codes, the N sum binary codes respectively indicating N results of comparing a sum signal of the pixel signal with the ramp signal, wherein N is an integer of 2 or more, and wherein the first image signal is output from some of pixels in each of the plurality of pixel groups, and the sum signal is output from each of the pixels included in each of the plurality of pixel groups.

2 . The counter of claim 1 , further comprising:
a parallel-input parallel-output (PIPO) circuit configured to latch a parallel input gray code in response to a result of comparing the pixel signal and the ramp signal, and to output a parallel output gray code; a parallel-input serial-output (PISO) circuit configured to convert the parallel output gray code into the binary code and to sequentially output a least significant bit of the binary code to a most significant bit of the binary code one by one; and a serial binary adder circuit configured to add one of the N reset binary codes and the first image binary code, and to add the N reset binary codes and the first to N-th sum binary codes.

3 . The counter of claim 2 , wherein the PISO circuit comprises:
a plurality of switches; and a plurality of XOR gates connected in series, each of the plurality of XOR gates comprising an output terminal, a first input terminal, and a second input terminal, wherein the output terminal of at least two of the plurality of XOR gates is connected to the first input terminal of an XOR gate of a next stage, wherein the plurality of switches are configured to connect the second input terminals of the plurality of XOR gates to the PIPO circuit in response to switch signals, respectively, wherein the first input terminal of an XOR gate corresponding to the most significant bit from among the plurality of XOR gates is configured to receive a reset control signal, and wherein the reset control signal is at a high level while the reset signal and the ramp signal are compared, is at a low level while the first image signal and the ramp signal are compared, and is at the low level while the sum signal and the ramp signal are compared.

4 . The counter of claim 2 , wherein the serial binary adder circuit comprises:
a full adder circuit comprising a first input terminal, a second input terminal configured to receive an output signal of the reset memory circuit, a carry-in terminal, a carry-out terminal, and a sum terminal; a first flip-flop configured to output an output signal of the sum terminal to the reset memory circuit; and a second flip-flop configured to feed an output signal of the carry-out terminal back to the carry-in terminal.

5 . The counter of claim 2 , wherein the reset memory circuit comprises:
a plurality of latches configured to latch an output signal of the serial binary adder circuit comprises; a plurality of switches; and a plurality of OR gates connected in series, each of the plurality of OR gates comprising an output terminal, a first input terminal, and a second input terminal, wherein the output terminal of at least two of the plurality of OR gates is connected to the first input terminal of an OR gate of a next stage, wherein the plurality of switches are configured to connect the second input terminals of the plurality of OR gates to output terminals of the plurality of latches, respectively, or to a ground, in response to switch signals, wherein the first input terminal of an OR gate corresponding to the most significant bit from among the plurality of OR gates is configured to receive a reset shifting signal, and wherein the output terminal of an OR gate corresponding to the least significant bit from among the plurality of OR gates is connected to the serial binary adder circuit.

6 . The counter of claim 5 , wherein, while the first image signal and the ramp signal are compared, a switch connected to the OR gate corresponding to the least significant bit from among the plurality of switches is turned off, and the reset memory circuit is configured to perform the shifting operation on the sum of the first to N-th reset binary codes in response to the reset shifting signal of a high level.

7 . An image sensor comprising:
a pixel array configured to generate a pixel signal and comprising a plurality of pixel groups, wherein each of the plurality of pixel groups comprises a first pixel comprising a first photoelectric conversion element and a second pixel comprising a second photoelectric conversion element; a ramp signal generator configured to generate a ramp signal; and an analog-to-digital converting circuit configured to convert the pixel signal into a digital signal, wherein the analog-to-digital converting circuit comprises:
a comparator configured to generate a first comparison signal by comparing a reset signal of the pixel signal with the ramp signal in a first period, a second comparison signal by comparing the reset signal of the pixel signal with the ramp signal in a second period, a third comparison signal by comparing a first image signal of the pixel signal with the ramp signal in a third period, a fourth comparison signal by comparing a sum signal of the pixel signal with the ramp signal in a fourth period and a fifth comparison signal by comparing the sum signal of the pixel signal with the ramp signal in a fifth period, wherein the first image signal is based on the first photoelectric conversion element, and the sum signal is based on both the first photoelectric conversion element and the second photoelectric conversion element; and
a counter circuit configured to generate a first binary code corresponding to the first comparison signal and a second binary code corresponding to the second comparison signal, to perform a shifting operation on a sum of a first reset binary code corresponding to the first comparison signal and a second reset binary code corresponding to the second comparison signal, and to generate the digital signal corresponding to the pixel signal based on a result of the shifting operation.

8 . The image sensor of claim 7 , wherein the counter circuit comprises:
a parallel-input parallel-output (PIPO) circuit configured to latch a parallel input gray code in response to the first comparison signal and the second comparison signal, and to output a parallel output gray code; a parallel-input serial-output (PISO) circuit configured to convert the parallel output gray code into a binary code and to sequentially output a least significant bit of the binary code to a most significant bit of the binary code one by one; a serial binary adder circuit configured to add the result of the shifting operation and a first image binary code corresponding to the third comparison signal, and to add the first reset binary code, the second reset binary code, a first sum code corresponding to the fourth comparison signal and a second sum code corresp

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hyeokjong

Classifications

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/704

  Pixels specially adapted for focusing, e.g. phase difference pixel sets · CPC title

• H04N25/75 Primary

  Circuitry for providing, modifying or processing image signals from the pixel array · CPC title

• H04N25/766

  comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power · CPC title

• H04N25/78 Primary

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title