Gray counter and image sensor including the same

Patent metadata

Field	Value
Publication number	US-11317047-B2
Application number	US-202016984661-A
Country	US
Kind code	B2
Filing date	Aug 4, 2020
Priority date	Nov 27, 2019
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

An image sensor includes a pixel sensor that senses an incident light and outputs a sampling signal of an analog shape, a sampler that compares the sampling signal and a ramp signal and outputs a comparison signal being time-axis length information, and a gray counter that counts a length of the comparison signal in synchronization with a clock signal and outputs a digital value. The gray counter includes a first flip-flop that divides the clock signal by 2 and generates a first gray code signal, a second flip-flop that delays a first data signal being a four-divided signal of the clock signal and outputs a second gray code signal, and a third flip-flop that delays the second gray code signal being two-divided and outputs a third gray code signal.

First claim

What is claimed is:

1. An image sensor, comprising:
a pixel sensor configured to sense an incident light and to output an analog sampling signal;
a sampler configured to compare the sampling signal and a ramp signal, and to output a comparison signal of time-axis length information; and
a gray counter configured to count a length of the comparison signal in synchronization with a clock signal, and to output a digital value, the gray counter including:
a first flip-flop configured to divide the clock signal by 2, and to generate a first gray code signal;
a second flip-flop configured to delay a first data signal, which is a four-divided signal of the clock signal, and to output a second gray code signal; and
a third flip-flop configured to delay the second gray code signal, which is two-divided, and to output a third gray code signal.

2. The image sensor as claimed in claim 1 , wherein the first flip-flop is triggered at a falling edge of the clock signal.

3. The image sensor as claimed in claim 1 , wherein the second flip-flop and the third flip-flop are triggered at a rising edge of the clock signal.

4. The image sensor as claimed in claim 1 , further comprising a Johnson counter implemented with a flip-flop, and configured to divide the clock signal by 4 and to generate the first data signal.

5. The image sensor as claimed in claim 4 , wherein the Johnson counter includes:
a fourth flip-flop triggered in response to the clock signal; and
a fifth flip-flop configured to receive data from an inverted data output terminal of the fourth flip-flop, and to output the first data signal to the second flip-flop in response to the clock signal, an inverted data output terminal of the fifth flip-flop being connected with a data input terminal of the fourth flip-flop.

6. The image sensor as claimed in claim 1 , wherein the gray counter further includes a sixth flip-flop configured to divide an inverted version of the second gray code signal by 2, and to provide a result of the division to the third flip-flop.

7. The image sensor as claimed in claim 1 , wherein the gray counter further includes:
a seventh flip-flop configured to divide and output an inverted version of the third gray code signal by 2;
an eighth flip-flop configured to delay and output an output of the seventh flip-flop as much as one period of the clock signal; and
a ninth flip-flop configured to delay an output of the eighth flip-flop as much as one period of the clock signal, and to output a fourth gray code signal.

8. The image sensor as claimed in claim 7 , wherein the gray counter further includes:
a tenth flip-flop configured to output an inverted version of the fourth gray code signal in synchronization with the clock signal that is four-divided; and
an eleventh flip-flop configured to delay and output an output of the tenth flip-flop as much as one period of the clock signal.

9. The image sensor as claimed in claim 1 , wherein a replica flip-flop circuit is configured as the first flip-flop for providing a signal delay corresponding to the second and third flip-flops.

10. A gray counter that generates a gray code count value in synchronization with a clock signal, the gray counter comprising:
a first flip-flop configured to divide the clock signal by 2, and to generate a first gray code signal corresponding to a least significant bit gray count value;
a Johnson counter configured to divide the clock signal by 4, and to output a first data signal;
a second flip-flop configured to delay the first data signal as much as a length corresponding to one period of the clock signal, and to output a second gray code signal;
a third flip-flop configured to divide the second gray code signal by 2, and to output a third gray code signal; and
a plurality of flip-flops configured to generate a count value above the third gray code signal using the clock signal and the third gray code signal.

11. The gray counter as claimed in claim 10 , wherein:
the first flip-flop is a D-flip-flop that is triggered at a falling edge of the clock signal, and
the D-flip-flop is implemented with a toggle flip-flop in which an inverted output terminal and a data input terminal are connected.

12. The gray counter as claimed in claim 10 , wherein each of the second flip-flop and the third flip-flop is a D-flip-flop that is triggered at a rising edge of the clock signal.

13. The gray counter as claimed in claim 10 , wherein the Johnson counter includes:
a fourth flip-flop triggered in response to the clock signal; and
a fifth flip-flop configured to receive data from an inverted data output terminal of the fourth flip-flop, and to output the first data signal to the second flip-flop in response to the clock signal, an inverted data output terminal of the fifth flip-flop being connected with a data input terminal of the fourth flip-flop.

14. The gray counter as claimed in claim 10 , further comprising a sixth flip-flop configured to divide an inverted version of the second gray code signal by 2, and to provide a result of the division to the third flip-flop.

15. The gray counter as claimed in claim 10 , wherein the gray code count value corresponds to a 5-bit value, and
wherein the plurality of flip-flops include:
a seventh flip-flop configured to divide and output an inverted version of the third gray code signal by 2;
an eighth flip-flop configured to delay and output an output of the seventh flip-flop as much as one period of the clock signal; and
a ninth flip-flop configured to delay an output of the eighth flip-flop as much as one period of the clock signal, and to output a fourth gray code signal;
a tenth flip-flop configured to output an inverted version of the fourth gray code signal in synchronization with the clock signal that is four-divided; and
an eleventh flip-flop configured to delay and output an output of the tenth flip-flop as much as one period of the clock signal.

16. The gray counter as claimed in claim 15 , wherein the four-divided clock signal input to the tenth flip-flop is provided using the Johnson counter.

17. A gray counter that generates a gray code count value in synchronization with a clock signal, the gray counter comprising:
a replica circuit configured to generate a first gray code signal corresponding to a least significant bit gray count value from a first clock signal, which is obtained by dividing the clock signal by 2;
a first flip-flop configured to delay a second clock signal, which is obtained by delaying the first clock signal as much as half a period of the clock signal, and to output a second gray code signal;
a Johnson counter triggered at the second clock signal, and configured to divide and output the second clock signal by 2;
a second flip-flop configured to delay an output of the Johnson counter as much as one period of the second clock signal, and to output a third gray code signal;
a third flip-flop configured to divide the third gray code signal by 2, and to output a fourth gray code signal; and
a plurality of flip-flops configured to generate a count value above the fourth gray code signal using the fourth gray code signal.

18. The gray counter as claimed in claim 17 , wherein the replica circuit delays the first clock signal as much as a clock to data delay of the first flip-flop or the second flip-flop.

19. The gray counter as claimed in claim 17 , wherein the first clock signal transitions at a rising edge of the clock signal, and the second clock signal transitions at a falling edge of the clock signal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Younghun
• Eom Jaeha
• Jung Seunghoon

Classifications

• H03M7/16 Primary

  Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code · CPC title

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/771

  comprising storage means other than floating diffusion · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title