Communication techniques with self-decodable redundancy versions (RVs) using systematic codes

Patent metadata

Field	Value
Publication number	US-12476733-B2
Application number	US-201816011530-A
Country	US
Kind code	B2
Filing date	Jun 18, 2018
Priority date	Jun 19, 2017
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

The present disclosure provides self-decodable redundancy versions for a systematic code. An apparatus for wireless communications includes at least one processor coupled with a memory and comprising encoder circuitry configured to encode a set of information bits using a systematic code to generate an encoded bit stream with information bits and parity bits, and bit ordering circuitry configured to re-order bits in the encoded bit stream to distribute the information bits and the parity bits. The apparatus includes a transmitter configured to transmit the re-ordered bits in accordance with a radio technology via one or more antenna elements situated proximate the receiver.

First claim

What is claimed is:

1 . An apparatus for wireless communications, comprising:
at least one processor coupled with a memory and comprising:
encoder circuitry configured to encode a set of information bits using a systematic code to generate an encoded bit stream with information bits and parity bits, wherein the systematic code comprises a lifted low-density parity-check (LDPC) code;
puncturing circuitry configured to puncture one or more information bits in the encoded bit stream according to a puncturing pattern; and
bit ordering circuitry configured to re-order bits in the encoded bit stream by interleaving the information bits with the parity bits to distribute the information bits and the parity bits in the encoded bit stream such that an equal number of check nodes, in the lifted LDPC code, having a single edge connected to a punctured information bit are included in transmissions associated with different redundancy versions (RVs); and
a transmitter configured to transmit the re-ordered bits in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximate the transmitter.

2 . The apparatus of claim 1 , wherein the lifted LDPC code includes a block diagonal hybrid automatic repeat request (HARQ) extension.

3 . The apparatus of claim 2 , wherein the transmission comprises a HARQ RV transmission that is not an RV 0 transmission.

4 . The apparatus of claim 1 , wherein the lifted LDPC code is restricted to a lifted LDPC code corresponding to a code rate higher than a lowest code rate associated with a base graph associated with the LDPC code.

5 . An apparatus for wireless communications, comprising:
at least one processor coupled with a memory and comprising:
encoder circuitry configured to encode a set of information bits using a systematic code to generate an encoded bit stream with information bits and parity bits;
bit ordering circuitry configured to re-order bits by interleaving the information bits with the parity bits in the encoded bit stream to distribute the information bits and the parity bits in the encoded bit stream, wherein the bit ordering circuitry is configured to re-order the bits in the encoded bit stream by:
if an original transmission code rate is below a threshold code rate, performing a random uniform re-ordering of the bits for a retransmission; and
if the original transmission code rate is above the threshold code rate:
re-ordering according to pre-determined pattern for the retransmission; and
selecting a starting bit for reading from a circular buffer; and

buffer management circuitry configured to:
store the re-ordered bit stream in the circular buffer; and
sequentially read the stored re-ordered bits from the circular buffer for the original transmission or retransmission; and

a transmitter configured to transmit the re-ordered bits in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximate the transmitter.

6 . The apparatus of claim 1 , wherein:
the at least one processor further comprises memory management circuitry configured to:
store the encoded bit stream in a buffer, and
re-order the bits in the encoded bit stream by reading the stored bits non-sequentially from the buffer.

7 . The apparatus of claim 1 , wherein the re-ordering is based on at least one of: the RV or a code rate associated with an original transmission or a retransmission of the set of information bits.

8 . The apparatus of claim 1 , wherein the bit ordering circuitry is configured to re-order groups of bits in the encoded bit stream.

9 . The apparatus of claim 8 , wherein each group of bits comprises Z information bits or Z parity bits.

10 . The apparatus of claim 1 , wherein the bit ordering circuitry is configured to:
re-order the bits in the encoded bit stream for a retransmission; and maintain an order of an encoded bit stream for an original transmission.

11 . The apparatus of claim 1 , wherein different retransmissions use a same or different re-ordering.

12 . An apparatus for wireless communications, comprising:
at least one processor coupled with a memory and comprising:
encoder circuitry configured to encode a set of information bits using a systematic code to generate an encoded bit stream with information bits and parity bits; and
bit ordering circuitry configured to re-order bits in the encoded bit stream by interleaving the information bits with the parity bits to distribute the information bits and the parity bits in the encoded bit stream, such that overlapping bits between transmissions or retransmissions associated with different redundancy versions (RVs) include a particular subset of the information bits such that the different transmissions and retransmissions are each self-decodable; and
a transmitter configured to transmit the re-ordered bits in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximate the transmitter.

13 . An apparatus for wireless communications by a receiving device, comprising:
a receiver configured to receive a transmission comprising an encoded bit stream with information bits and parity bits in accordance with a radio technology across a wireless channel via one or more antenna elements situated proximate the receiver; and at least one processor coupled with a memory and comprising:
bit ordering circuitry configured to re-order bits in the encoded bit stream by deinterleaving the information bits with the parity bits to distribute the information bits and the parity bits in an original bit sequence;
depuncturing circuitry configured to depuncture one or more information bits in the encoded bit stream according to a puncturing pattern after the re-ordering; and
decoder circuitry configured to decode the re-ordered bits using a systematic code to obtain a set of information bits, wherein the systematic code comprises a lifted low-density parity-check (LDPC) code, and wherein an equal number of check nodes, in the lifted LDPC code, having a single edge connected to a punctured information bit are included in transmissions associated with different redundancy versions (RVs).

14 . The apparatus of claim 13 , wherein the lifted LDPC code has a block diagonal hybrid automatic repeat request (HARQ) extension.

15 . The apparatus of claim 13 , wherein:
the receiver is further configured to receive an indication of a re-ordering used by a transmitting device; and the bit ordering circuitry is configured to re-order the bits based on the indication.

16 . The apparatus of claim 13 , wherein the bit ordering circuitry is configured to:
re-order the bits in the encoded bit stream for a retransmission; and maintain an order of an encoded bit stream for an original transmission.

17 . The apparatus of claim 13 , wherein different retransmissions use a same or different re-ordering.

18 . A method for wireless communications by a transmitting device, comprising:
encoding a set of information bits using a systematic code to generate an encoded bit stream with information bits and parity bits; re-ordering bits in the encoded bit stream by interleaving the information bits with the parity bits to distribute the information bits and the parity bits in the encoded bit stream by:
if an original transmission code rate is below a threshold code rate, performing a random uniform re-ordering of the bits for a retransmission; and
if the original transmission code rate is above a thresh

Assignees

• Qualcomm Inc

Inventors

• Soriaga Joseph Binamira
• KUDEKAR Shrinivas
• Richardson Thomas
• Sarkis Gabi
• Sankar Hari
• Jiang Jing

Classifications

• H03M13/116

  Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices · CPC title

• H04L1/0069

  Puncturing patterns · CPC title

• H04L1/1841

  Resequencing · CPC title

• H03M13/616

  Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations · CPC title

• H04L1/1819

  with retransmission of additional or different redundancy · CPC title