Forward error correction decoder and method therefor

Patent metadata

Field	Value
Publication number	US-9325347-B1
Application number	US-201414186786-A
Country	US
Kind code	B1
Filing date	Feb 21, 2014
Priority date	Feb 21, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A Forward Error Correction (FEC) decoder is provided, for example including a Layered Low Density Parity Check (LDPC) component. In an implementation, power consumption of the LDPC decoder is minimized with minimal to no impact on the error correction performance. This is achieved, in an implementation, by partially or fully eliminating redundant operations in the iterative process.

First claim

What is claimed is:

1. An iterative forward error correction (FEC) decoder configured to perform a set of decoding operations during a selected FEC decode, comprising:
a main memory configured to receive an input and to transmit an output;
a plurality of check node convergence testers;
a plurality of layer processors, each layer processor comprising:
a check node configured to receive a signal based on the main memory output, and to process the received signal based on a message passing method; and
a unique check node convergence tester, from among the plurality of check node convergence testers, configured to test for convergence on the check node;
wherein the layer processor performs only a subset of the set of decoding operations of the layer processor in response to a determination that the check node of the layer processor has converged;

wherein the plurality of check node convergence testers is equal in number to the plurality of layer processors;
an adder in communication with the check node and configured to receive a check node output to combine extrinsic information generated by the check node with channel information for the layer and provide the combined information to the main memory for storage for an update; and
a delay element configured to feed back the extrinsic information from the check node output for processing in the next iteration;
wherein the check node convergence tester is configured to disable a write-back operation to the delay element when the check node has converged.

2. The decoder of claim 1 wherein the FEC decoder comprises a layered iterative low density parity check (LDPC) decoder, and wherein the set of decoding operations is performed during a selected LDPC decode.

3. The decoder of claim 1 wherein the check node convergence tester is configured to disable a portion of the layer processor when the check node has converged.

4. The decoder of claim 1 wherein the check node convergence tester is configured to disable a write-back operation to the main memory when the check node has converged.

5. The decoder of claim 1 further comprising an adaptive processing controller configured to receive an output from the check node convergence tester and to provide an output to the main memory.

6. The decoder of claim 5 wherein the adaptive processing controller comprises a memory element that stores row convergence information from the plurality of check node convergence testers.

7. The decoder of claim 5 wherein the check node convergence tester is configured to omit processing of nodes having a high probability of resulting in no net benefit to convergence.

8. The decoder of claim 5 wherein the adaptive processing controller further comprises control circuitry configured to periodically, according to configuration parameters, disable low-power operations.

9. The decoder of claim 5 wherein the adaptive processing controller skips a current processing step and advances to the next processing step in response to a determination by the check node convergence tester that all rows of a current processing step are marked as converged in the adaptive control memory.

10. The decoder of claim 5 wherein the decoder gates off a check node in response to a determination by the check node convergence tester that all rows in the check node have converged.

11. The decoder of claim 5 wherein the decoder gates off all updates for any row that has converged, in response to a determination by the check node convergence tester that neither the entire processing step has converged nor the rows in the current check node have converged.

12. A decoding method for an iterative forward error correction (FEC) decoder having a plurality of layer processors and a plurality of check node convergence testers, the plurality of check node convergence testers being equal in number to the plurality of layer processors, each of the plurality of layer processors comprising a check node, and adder in communication with the check node, a delay element, and a unique one of the plurality of check node convergence testers, the method comprising:
for each of the plurality of layer processors:
receiving, at the check node of the layer processor, a signal based on a main memory output;
processing, at the check node, the received signal based on a message passing method; and
determining, at the check node convergence tester of the layer processor, whether the check node has converged; and

when the FEC decoder is configured to perform a set of decoding operations during a selected FEC decode, for each layer processor for which the check node is determined to have converged:
performing only a subset of the set of decoding operations of the layer processor in response to a determination that the check node of the layer processor has converged;
at the adder in communication with the check node:
receiving a check node output;
combining extrinsic information generated by the check node with channel information for the layer; and
providing the combined information to the main memory for storage for an update;

feeding back, by the delay element, the extrinsic information from the check node output for processing in the next iteration; and
disabling, using the check node convergence tester, a write-back operation to the delay element when the check node has converged.

13. The method of claim 12 wherein the FEC decoder comprises a layered iterative low density parity check (LDPC) decoder, and wherein the subset of the set of decoding operations is performed during a selected LDPC decode.

14. The method of claim 12 further comprising disabling, using the check node convergence tester, a portion of the layer processor when the check node has converged.

15. The method of claim 12 further comprising disabling, using the check node convergence tester, a write-back operation to the main memory when the check node has converged.

16. The method of claim 12 further comprising receiving, at an adaptive processing controller, an output from the check node convergence tester and providing an output to the main memory.

17. The method of claim 12 further comprising omitting processing, at the check node convergence tester, of nodes having a high probability of resulting in no net benefit to convergence.

Assignees

• Pmc Sierra Us Inc
• Microsemi Storage Solutions U S Inc

Inventors

• Graumann Peter
• Gibb Sean

Classifications

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• G11B20/1833

  by adding special lists or symbols to the coded information (G11B20/1806, G11B20/1866 take precedence) · CPC title

• H04L1/0061

  Error detection codes · CPC title

• H04L1/0041

  Arrangements at the transmitter end · CPC title

• H04L1/0057 Primary

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title