Integrated circuit generation using an integrated circuit shell

Patent metadata

Field	Value
Publication number	US-12475284-B2
Application number	US-202217992976-A
Country	US
Kind code	B2
Filing date	Nov 23, 2022
Priority date	Dec 17, 2021
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

Systems and methods are disclosed for integrated circuit design using integrated circuit shells. For example, a system may generate an integrated circuit core design expressed in a hardware description language. The integrated circuit core design may express circuitry that describes one or more functions to be included in an application specific integrated circuit (ASIC). The one or more functions may have connection points providing first inputs and outputs to the one or more functions. The system may query an integrated circuit shell expressed in a hardware description language. The integrated circuit shell may express circuitry that describes a limited set of pads to be implemented in the ASIC. The limited set of pads may provide second inputs and outputs to the integrated circuit. The query may determine availability of pads of the limited set of pads to connect to the connection points of the one or more functions.

First claim

What is claimed is:

1 . A method comprising:
generating an integrated circuit core design expressed in a hardware description language, the integrated circuit core design expressing circuitry that describes one or more functions to be included in an application specific integrated circuit (ASIC), wherein the one or more functions have connection points providing first inputs and outputs to the one or more functions; and querying an integrated circuit shell expressed in a hardware description language, the integrated circuit shell expressing circuitry that describes a limited set of pads to be implemented in the ASIC, the limited set of pads providing second inputs and outputs to the ASIC, wherein the querying determines availability of pads of the limited set of pads to connect to connection points of the one or more functions.

2 . The method of claim 1 , further comprising mapping available pads of the limited set of pads to the connection points of the one or more functions.

3 . The method of claim 1 , further comprising generating an integrated circuit design expressed in a hardware description language using the integrated circuit core design and the integrated circuit shell, wherein the integrated circuit design corresponds to an ASIC that is a system on a chip (SoC).

4 . The method of claim 1 , further comprising generating the integrated circuit shell.

5 . The method of claim 1 , further comprising selecting the integrated circuit shell from a plurality of integrated circuit shells, wherein integrated circuit shells of the plurality of integrated circuit shells have different configurations for the limited set of pads.

6 . The method of claim 1 , further comprising selecting the integrated circuit shell from a plurality of integrated circuit shells based on the integrated circuit shell having available pads mapping to the connection points of the one or more functions.

7 . The method of claim 1 , wherein the limited set of pads comprises one or more groups of pads, and wherein the querying determines availability of a group of pads for connecting to the connection points of a function of the one or more functions.

8 . The method of claim 1 , wherein querying the integrated circuit shell comprises executing an application program interface to determine the availability of pads.

9 . The method of claim 1 , wherein the one or more functions is selected from a group consisting of double data rate (DDR) memory; peripheral component interconnect express (PCIe); general purpose inputs and outputs (GPIOs); universal asynchronous receiver-transmitter (UART); serial peripheral interface (SPI); pulse-width modulation (PWM); and inter-integrated circuit (I 2 C).

10 . A system comprising:
a memory; and a processor, wherein the memory includes instructions executable by the processor to cause the system to: generate an integrated circuit core design expressed in a hardware description language, the integrated circuit core design expressing circuitry that describes one or more functions to be included in an ASIC, wherein the one or more functions have connection points providing first inputs and outputs to the one or more functions; and query an integrated circuit shell expressed in a hardware description language, the integrated circuit shell expressing circuitry that describes a limited set of pads to be implemented in the ASIC, wherein the limited set of pads provides second inputs and outputs to the ASIC, wherein the query determines availability of pads of the limited set of pads to connect to the connection points of the one or more functions.

11 . The system of claim 10 , wherein the memory includes instructions executable by the processor to cause the system to map available pads of the limited set of pads to the connection points of the one or more functions.

12 . The system of claim 10 , wherein the memory includes instructions executable by the processor to cause the system to generate an integrated circuit design expressed in a hardware description language using the integrated circuit core design and the integrated circuit shell, wherein the integrated circuit design corresponds to an ASIC that is a SoC.

13 . The system of claim 10 , wherein the memory includes instructions executable by the processor to cause the system to generate the integrated circuit shell.

14 . The system of claim 10 , wherein the memory includes instructions executable by the processor to cause the system to select the integrated circuit shell from a plurality of integrated circuit shells, wherein integrated circuit shells of the plurality of integrated circuit shells have different configurations for the limited set of pads.

15 . The system of claim 10 , wherein the memory includes instructions executable by the processor to cause the system to select the integrated circuit shell from a plurality of integrated circuit shells based on the integrated circuit shell having available pads mapping to the connection points of the one or more functions.

16 . A non-transitory computer-readable storage medium that includes instructions that, when executed by a processor, causes the processor to:
generate an integrated circuit core design expressed in a hardware description language, the integrated circuit core design expressing circuitry that describes one or more functions to be included in an ASIC, wherein the one or more functions have connection points providing first inputs and outputs to the one or more functions; and query an integrated circuit shell expressed in a hardware description language, the integrated circuit shell expressing circuitry that describes a limited set of pads to be implemented in the ASIC, wherein the limited set of pads provides second inputs and outputs to the ASIC, wherein the query determines availability of pads of the limited set of pads to connect to the connection points of the one or more functions.

17 . The non-transitory computer-readable storage medium of claim 16 , further comprising instructions that, when executed by a processor, causes the processor to map available pads of the limited set of pads to the connection points of the one or more functions.

18 . The non-transitory computer-readable storage medium of claim 16 , further comprising instructions that, when executed by a processor, causes the processor to generate an integrated circuit design expressed in a hardware description language using the integrated circuit core design and the integrated circuit shell, wherein the integrated circuit design corresponds to an ASIC that is a SoC.

19 . The non-transitory computer-readable storage medium of claim 16 , further comprising instructions that, when executed by a processor, causes the processor to generate the integrated circuit shell.

20 . The non-transitory computer-readable storage medium of claim 16 , further comprising instructions that, when executed by a processor, causes the processor to select the integrated circuit shell from a plurality of integrated circuit shells, wherein integrated circuit shells of the plurality of integrated circuit shells have different configurations for the limited set of pads.

Assignees

• Sifive Inc

Inventors

• Macdonald Ryan
• Danie Erik Arthur
• Terpstra Wesley Waylon
• Lee Yunsup

Classifications

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F2113/18

  Chip packaging · CPC title

• G06F30/31 Primary

  Design entry, e.g. editors specifically adapted for circuit design · CPC title