Memory device, memory controller, and memory system including the same

Patent metadata

Field	Value
Publication number	US-12474874-B2
Application number	US-202318340950-A
Country	US
Kind code	B2
Filing date	Jun 26, 2023
Priority date	Aug 12, 2020
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

A memory system includes a first memory device including a plurality of first memory blocks each including a plurality of first memory cells stacked in a direction perpendicular to a substrate; and a memory controller configured to control a memory operation of the first memory device. The memory controller is configured to select and operate any one of different control schemes for each of the first memory blocks based on a number of first not-open (N/O) strings included in each of the first memory blocks, respectively.

First claim

What is claimed is:

1 . A memory system comprising:
a first memory device comprising a plurality of first memory blocks of a same type, each including a plurality of first memory cells stacked in a direction perpendicular to a substrate; and a memory controller configured to control a memory operation of the first memory device, wherein the memory controller is configured to designate any one of a plurality of types of memory blocks having different data reliability guarantees to each of the plurality of first memory blocks based on a number of first not-open (N/O) strings in each of the plurality of first memory blocks, and operate the plurality of first memory blocks based on the designation by the memory controller with respect to the plurality of first memory blocks, wherein each of the first N/O strings has a defect in which a channel is not formed in each of the first N/O strings.

2 . The memory system of claim 1 , wherein the plurality of types of memory blocks includes a first type of memory block and a second type of memory block ensuring higher data reliability than the first type of memory block, and
wherein the memory controller is further configured to designate a first target memory block having the number of the first N/O strings equal to or greater than a threshold value from among the first memory blocks as the first type of memory block and to designate a second target memory block having the number of the first N/O strings less than the threshold value from among the first memory blocks as the second type of memory block having higher data reliability than the first type of memory block.

3 . The memory system of claim 2 , wherein the second type of memory block is operated as a single level cell, and the first type of memory block is operated as any one of a multi level cell, a triple level cell, and a quad level cell.

4 . The memory system of claim 2 , wherein the first type of memory block is operated, such that cold data, which is accessed less frequently than a reference frequency, is written thereto, and
the second type of memory block is operated, such that hot data, which is accessed more frequently than the reference frequency, is written thereto.

5 . The memory system of claim 1 , wherein information indicating the number of first N/O strings is provided to the memory controller from the first memory device.

6 . The memory system of claim 1 , wherein information indicating the number of first N/O strings is generated during a test of the first memory device.

7 . The memory system of claim 6 , wherein the information indicating the number of first N/O strings is stored in some of the first memory cells or latches included in a peripheral circuit of the first memory device.

8 . The memory system of claim 7 , wherein the memory controller further comprises an internal memory configured to store the first N/O string information.

9 . The memory system of claim 1 , further comprising a second memory device comprising a plurality of second memory blocks each including a plurality of second memory cells stacked in a direction perpendicular to the substrate, and
wherein the memory controller is configured to designate any one of the plurality of types of memory blocks to each of the second memory blocks based on a number of second N/O strings in each of the second memory blocks, and operate the plurality of second memory blocks based on a designation result of the plurality of second memory blocks.

10 . The memory system of claim 9 , wherein the memory controller is further configured to back-up designation information indicating the designation result in the first memory device.

11 . The memory system of claim 10 , wherein the designation information is provided to the memory controller from the first memory device when the memory system is powered on after being powered off.

12 . A memory controller comprising:
an internal memory configured to store not-open (N/O) string information regarding a number of N/O strings included in each of a plurality of memory blocks of a same type included in an external memory device; and a processor configured to, based on the N/O string information, operate first target memory blocks, including at least one N/O string, from among the plurality of memory blocks as a first type of memory block and to operate second target memory blocks, from among the plurality of memory blocks, without any N/O strings as a second type of memory block of the external memory device that guarantees higher reliability than the first type of memory block wherein each of the N/O strings has a defect in which a channel is not formed in each of the N/O strings.

13 . The memory controller of claim 12 , wherein the processor is further configured to operate the second target memory block as a lower level cell than a level of cells within the first target memory block.

14 . The memory controller of claim 12 , wherein the second type of memory block is operated as a single level cell, and
the first type of memory block is operated as any one of a multi level cell, a triple level cell, and a quad level cell based on a number of the N/O strings of the first target memory blocks.

15 . The memory controller of claim 12 , wherein the first target memory blocks are operated, such that cold data, which is accessed less frequently than a reference frequency, is written thereto, and
the second target memory blocks are operated, such that hot data, which is accessed more frequently than the reference frequency, is written thereto.

16 . The memory controller of claim 12 , wherein the processor is further configured to request the N/O information from the external memory device and receive the N/O string information from the external memory device.

17 . The memory controller of claim 12 , wherein the processor is further configured to back up information indicating an operation scheme for the plurality of memory blocks in the external memory device.

18 . A memory system comprising:
a memory device comprising a plurality of memory blocks each including a plurality of memory cells stacked in a direction perpendicular to a substrate; and a memory controller configured to control a memory operation of the memory device, wherein the memory controller is configured to generate a first type of program command for a first target memory block, having a number of not open (N/O) strings equal to or greater than a threshold value, from among the plurality of memory blocks, and provide the first type of program command to the memory device, wherein the memory device is configured to, in response to the first type of program command, perform a program operation on the first target memory block including an operation of detecting the N/O strings in the first target memory block and a data conversion operation based on a detection result of detecting N/O strings in the first target memory block, wherein the data conversion operation converts a plurality of bits of target data previously intended to be written to a plurality of target memory cells included in a detected N/O string to have predetermined values, and wherein each of the N/O strings has a defect in which a channel is not formed in each of the N/O strings.

19 . The memory system of claim 18 , wherein the memory controller is further configured to generate a second type of program command for a second target memory block having the number of N/O strings less than the threshold value from among the first memory blocks, and provi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Wontaeck
• Kim Bohchang
• Ko Kuihan
• Jeong Jaeyong

Classifications

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title