Platform voltage regulator circuitry configurations

Patent metadata

Field	Value
Publication number	US-12474759-B2
Application number	US-202217683435-A
Country	US
Kind code	B2
Filing date	Mar 1, 2022
Priority date	Mar 1, 2022
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

An apparatus, system, and method for improved thermal design power (TDP) range are provided. A device includes a first voltage regulator configured to provide first voltage of a first voltage value, a second voltage regulator configured to provide a second voltage of a second, different voltage value, a first capacitor electrically coupled between a first output of the first voltage regulator and a ground, a second capacitor electrically coupled between a second output of the second voltage regulator and the ground, a first switch electrically coupled between the first output and the second output, a second switch situated in parallel with the first switch, the second switch electrically coupled between the first output and the second output, and a controller configured to provide control signals that control the first voltage regulator, the second voltage regulator, the first switch, and the second switch.

First claim

What is claimed is:

1 . A device comprising:
a first voltage regulator configured to provide a first VR output; a second voltage regulator configured to provide a second VR output independent of the first VR output; a first capacitor electrically coupled between the first VR output and a ground; a second capacitor electrically coupled between the second VR output and the ground; a first switch electrically coupled between the first VR output and the second VR output; a second switch situated in parallel with the first switch, the second switch electrically coupled between the first VR output and the second VR output; and a controller configured to provide control signals that control the first voltage regulator, the second voltage regulator, the first switch, and the second switch, wherein the first switch and the second switch are situated, when activated, to reduce parasitic output resistance and parasitic output inductance of the first voltage regulator to a load.

2 . The device of claim 1 , wherein the first switch and the second switch are situated to, when activated, make the first and second capacitors electrically in parallel to each other.

3 . The device of claim 1 , wherein the controller is configured to:
receive a signal indicating a processor coupled to the first and second outputs is in a low power mode; and responsive to receiving the low power signal, activate the first and second switches.

4 . The device of claim 1 , wherein the first voltage regulator includes first inductors, and the second voltage regulator includes second inductors, wherein the controller is configured to:
receive a signal indicating a processor coupled to the first and second VR outputs is in a low power mode; and responsive to receiving the signal, turn off the first voltage regulator or the second voltage regulator.

5 . The device of claim 4 , wherein the controller is further configured to responsive to receiving the signal, activate only one inductor of the first inductors and the second inductors of the voltage regulator that is turned on.

6 . The device of claim 5 , wherein the only one inductor is an inductor that includes a physically shortest electrical path to a processor coupled to the first and second VR outputs.

7 . A device comprising:
a first voltage regulator configured to provide a first VR output; a second voltage regulator configured to provide a second VR output; a first capacitor electrically coupled between the first VR output and a ground; a second capacitor electrically coupled between the second VR output and the ground; a first switch electrically coupled between the first VR output and the second VR output; and a second switch situated in parallel with the first switch, the second switch electrically coupled between the first VR output and the second VR output, wherein the first switch and the second switch are situated, when activated, to reduce parasitic output resistance and parasitic output inductance of the first and second VR outputs coupled to a common load.

8 . The device of claim 7 , wherein the first switch and second switch are electrically coupled to receive a control signal from a controller.

9 . The device of claim 8 , wherein the control signal is asserted when a processor is the load coupled to the first and second VR outputs and is in a low power mode and causes the first VR output and the second VR output to short to each other.

10 . The device of claim 9 , wherein the control signal is asserted only when the processor is in the low power mode.

11 . The device of claim 7 , wherein the first switch and the second switch are situated to, when activated, make the first and second capacitors electrically in parallel to each other.

12 . A device comprising:
a first voltage regulator including a first VR output that is coupled to a processor; a second voltage regulator including a second VR output that is coupled to the processor; a first capacitor electrically coupled between the first VR output and a ground; a second capacitor electrically coupled between the second VR output and the ground; a first switch electrically coupled between the first VR output and the second VR output; a second switch disposed in parallel with the first switch across the first and second VR outputs, The first and second switches being spaced apart from one another through conductive traces, the first and second switches, when closed, reducing parasitic inductances and resistances from the conductive traces.

13 . The device of claim 12 , wherein the first voltage regulator includes first inductors, and the second voltage regulator includes second inductors, wherein a controller is configured to:
receive a signal indicating the processor coupled to the first and second VR outputs is in a low power mode; and responsive to receiving the signal, turn off the first voltage regulator or the second voltage regulator.

14 . The device of claim 13 , wherein the controller, responsive to receiving the signal, is configured to activate only one inductor of the first inductors and the second inductors of the voltage regulator that is turned on.

15 . The device of claim 14 , wherein the only one inductor is an inductor that includes a physically shortest electrical path to a processor coupled to the first and second VR outputs.

Assignees

• Intel Corp

Inventors

• Shekhar Sameer
• Jain Amit K
• Kuan Chin Lee

Classifications

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title