Method of manufacturing a semiconductor device having three-dimensional cell structure

Patent metadata

Field	Value
Publication number	US-12471509-B2
Application number	US-202318320144-A
Country	US
Kind code	B2
Filing date	May 18, 2023
Priority date	Oct 29, 2020
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A method of manufacturing a semiconductor device comprises: providing a substrate having a base insulation layer; forming, over the base insulation layer, a plurality of first word line structures extending in a first lateral direction and a first switching functional layer disposed between the plurality of first word line structures, the plurality of first word line structures; forming a first interlayer insulation layer on the plurality of first word line structures and the first switching functional layer; forming a plurality of second word line structures and a second switching functional layer disposed between the plurality of second word line structures; performing selective etching to the second switching functional layer, the first interlayer insulation layer, the first switching functional layer, and the base insulation layer to form bit line contact holes; and providing a conductive material in the bit line contact holes to form bit line structures.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
providing a substrate having a base insulation layer; forming, over the base insulation layer, a plurality of first word line structures extending in a first lateral direction parallel to a surface of the substrate and a first switching functional layer disposed between the plurality of first word line structures, the plurality of first word line structures being spaced apart from each other in a second lateral direction, which is parallel to the surface of the substrate and perpendicular to the first lateral direction; forming a first interlayer insulation layer on the plurality of first word line structures and the first switching functional layer; forming, on the first interlayer insulation layer, a plurality of second word line structures extending in the first lateral direction and a second switching functional layer disposed between the plurality of second word line structures, the plurality of second word line structures arranged to overlap with the plurality of first word line structures, respectively; performing selective etching to the second switching functional layer, the first interlayer insulation layer, the first switching functional layer, and the base insulation layer to form bit line contact holes exposing the substrate and to leave some portions of the first and second switching functional layers that remain on side surfaces of the plurality of first and second word line structures; and providing a conductive material in the bit line contact holes to form bit line structures.

2 . The method of claim 1 , wherein forming the bit line contact holes comprises forming the bit line contact holes to be arranged spaced apart from each other along the first lateral direction.

3 . The method of claim 1 , further comprising:
selectively etching the second switching functional layer, the first interlayer insulation layer, and the first switching functional layer to form cell insulation contact holes exposing the base insulation layer; and filling the cell insulation contact holes with an insulation material to form cell insulation structures.

4 . The method of claim 3 , wherein forming the cell insulation contact holes is performed before forming the bit line contact holes, and
wherein the cell insulation contact holes are formed to expose the first and second switching functional layers and the first interlayer insulation layer in the first lateral direction, and to expose the plurality of first and second word line structures and the first interlayer insulation layer in the second lateral direction.

5 . The method of claim 3 , wherein forming the cell insulation contact holes is performed after forming the bit line structures, and
wherein the cell insulation contact holes are formed to expose the first and second switching functional layers, the first interlayer insulation layer, and the bit line structures in the first lateral direction, and to expose the plurality of first and second word line structures and the first interlayer insulation layer in the second lateral direction.

6 . The method of claim 1 , wherein forming the plurality of first word line structures and the first switching functional layer comprises:
forming a conductive material layer on the base insulation layer; patterning the conductive material layer to form the plurality of first word line structures extending in the first lateral direction on the base insulation layer; forming a switching material layer to fill spaces between the plurality of first word line structures on the base insulation layer by a sputtering method, the switching material layer comprising a chalcogenide-based material; and planarizing the switching material layer over the base insulation layer to form the first switching functional layer positioned at the same level as the plurality of first word line structures.

7 . The method of claim 1 , wherein forming the plurality of second word line structures and the second switching functional layer comprises:
forming a conductive material layer on the first interlayer insulation layer; patterning the conductive material layer to form the plurality of second word line structures extending in the first lateral direction on the first interlayer insulation layer; and forming a switching material layer filling spaces between the plurality of second word line structures on the first interlayer insulation layer by a sputtering method, the switching material layer including a chalcogenide-based material; and planarizing the switching material layer on the first interlayer insulation layer to form the second switching functional layer positioned at the same level as the plurality of second word line structures.

8 . The method of claim 1 , wherein forming the bit line contact holes further comprises forming a first switching layer and a second switching layer from the some portions of the first and second switching functional layers that remain on the side surfaces of the plurality of first and second word line structures after the selective etching.

9 . The method of claim 8 , wherein in forming the bit line contact holes, the selective etching is performed such that the thicknesses of the first and second switching layers are substantially the same in the second lateral direction.

10 . The method of claim 1 , wherein forming the bit line contact holes comprises forming a polymer layer containing carbon (C) on surfaces of the first and second switching functional layer exposed along side surfaces of the bit line contact holes.

11 . The method of claim 1 , wherein forming the bit line contact holes comprises forming the bit line contact holes such that the side surface of each of the bit line contact holes has an acute inclination angle with respect to the surface of the substrate.

12 . The method of claim 1 , further comprising forming a second interlayer insulation layer on the plurality of second word line structures and the second switching material layer after forming the plurality of second word line structures and the second switching material layer,
wherein forming the bit line contact holes further comprises selectively etching the second interlayer insulation layer.

Assignees

• Sk Hynix Inc

Inventors

• Han Jae Hyun

Classifications

• H10N70/8845

  Carbon or carbides · CPC title

• H10N70/8825

  Selenides, e.g. GeSe · CPC title

• H10N70/882

  Compounds of sulfur, selenium or tellurium, e.g. chalcogenides · CPC title

• H10N70/061

  Shaping switching materials · CPC title

• H10N70/021

  Formation of switching materials, e.g. deposition of layers · CPC title