Low defect, high mobility thin film transistors with in-situ doped metal oxide channel material

Patent metadata

Field	Value
Publication number	US-12471318-B2
Application number	US-202117308856-A
Country	US
Kind code	B2
Filing date	May 5, 2021
Priority date	May 5, 2021
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Transistors with metal oxide channel material that is in-situ doped for desired charge carrier concentrations. The metal oxide channel material may be deposited by atomic layering of multiple constituent metals with an oxidation of each layer. Such an ALD process may be performed by cyclically depositing a precursor of one of the metals upon a substrate during a deposition phase, and oxidizing the absorbed precursor during an oxidation phase. For a quinary metal oxide, each of three metal precursors may be introduced and oxidized during the ALD process, and charge carrier concentrations may be modulated by further introducing a fourth metal precursor during the ALD process in a manner that disperses this dopant metal within the film at a significantly lower chemical concentration than the other metals.

First claim

What is claimed is:

1 . A transistor structure, comprising:
a first source or drain contact; a gate electrode material layer over the first source or drain contact; a gate insulator lining a via through a thickness of the gate electrode material layer and in contact with a sidewall of the gate electrode material layer; a channel material comprising a first portion lining a sidewall of the gate insulator within the via and a second portion over, and in contact with, the first source or drain contact at a bottom of the via, the first and second portions of the channel material comprising O, In, Ga, Zn, and Al with an atomic composition ratio of Ga to each of In and Zn of 1.5-2.5, and an atomic composition ratio of Ga to Al of 8-50, the first portion of the channel material of a first layer thickness, and the second portion of the channel material of a second layer thickness, wherein the first layer thickness is within 5% of the second layer thickness; and a second source contact or drain contact electrically coupled to the channel material.

2 . The transistor structure of claim 1 , wherein the Ga:In:Zn atomic ratio is 1.5-2.5:0.75-1.25:0.75-1.25, and wherein Al is no more than 5 at. % of all metals present in the channel material.

3 . The transistor structure of claim 1 , wherein Al is at least 1 at. % of all metals present in the channel material.

4 . The transistor structure of claim 1 , wherein each of In and Zn is least 20 at. % of all metals present in the channel material.

5 . The transistor structure of claim 1 , wherein Ga is 40-50 at. % of all metals present in the channel material and each of In and Zn is less than 25 at. % of all metals present in the channel material.

6 . The transistor structure of claim 1 , wherein the gate insulator comprises O and at least one of Hf or Al.

7 . An integrated circuit (IC) die, comprising:
a plurality of complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) structures, wherein individual ones of the CMOS FET structures comprise a Group IV semiconductor material; and a plurality of thin film transistor (TFT) structures over the CMOS FET structures, with one or more levels of interconnect metallization therebetween, wherein individual ones of the TFT structures comprise the transistor structure of claim 1 .

8 . A transistor structure, comprising:
a first source or drain contact; a gate electrode material layer adjacent to, and at a level above, the first source or drain contact, a gate insulator comprising a first portion lining a sidewall of the gate electrode material layer and a second portion over the first source or drain contact; a channel material comprising a first portion lining a sidewall of the first portion of the gate insulator and a second portion over the second portion of the gate insulator, the first and second portions of the channel material comprising O, In, Ga, Zn, and Al with an atomic composition ratio of Ga to each of In and Zn of 1.5-2.5, and an atomic composition ratio of Ga to Al of 8-50, the first portion of the channel material of a first layer thickness, and the second portion of the channel material of a second layer thickness, wherein the first layer thickness is within 5% of the second layer thickness; and a second source contact or drain contact electrically coupled to the channel material.

9 . The transistor structure of claim 8 , wherein the Ga: In:Zn atomic ratio is 1.5-2.5:0.75-1.25:0.75-1.25, and wherein Al is no more than 5 at. % of all metals present in the channel material.

10 . The transistor structure of claim 8 , wherein Al is at least 1 at. % of all metals present in the channel material.

11 . The transistor structure of claim 8 , wherein each of In and Zn is least 20 at. % of all metals present in the channel material.

12 . The transistor structure of claim 8 , wherein Ga is 40-50 at. % of all metals present in the channel material and each of In and Zn is less than 25 at. % of all metals present in the channel material.

13 . The transistor structure of claim 8 , wherein the gate insulator comprises O and at least one of Hf or Al.

Assignees

• Intel Corp

Inventors

• Ku Chieh-Jen
• Baran Andre
• Sell Bernhard
• Goldstein David
• Jen Timothy

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/203

  using transformation of metal, e.g. oxidation or nitridation · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3426 Primary

  Oxides · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title