Play mute circuit and method

Patent metadata

Field	Value
Publication number	US-12470187-B2
Application number	US-202217747845-A
Country	US
Kind code	B2
Filing date	May 18, 2022
Priority date	May 18, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

In an embodiment, an amplifier circuit includes a second stage that includes a first switch circuit including first and second terminals, a plurality of resistive elements coupled between the first and second terminals of the first switch circuit, and a plurality of switches configured to control an equivalent resistance between the first and second terminals of the first switch circuit. During play mode, the second stage has a gain between the input of the second stage and the output of the second stage of a first value. During a transition from mute mode to play mode, the amplifier circuit is configured to progressively increase the gain of the second stage from a second value to the first value. During a transition from play mode to mute mode, the amplifier circuit is configured to progressively decrease the gain of the second stage from the first value to the second value.

First claim

What is claimed is:

1 . An amplifier circuit configured to operate in a play mode and a mute mode, the amplifier circuit comprising:
an input stage configured to receive an input signal; and a second stage having an input coupled to an output of the input stage, the second stage comprising a first switch circuit comprising first and second terminals, a plurality of resistive elements coupled between the first and second terminals of the first switch circuit, and a plurality of switches configured to control an equivalent resistance between the first and second terminals of the first switch circuit, wherein:
each resistive element of the plurality of resistive elements has a resistance value different from each other resistive element, wherein the resistance values are configured such that, in response to all of the plurality of switches being closed, the equivalent resistance of the plurality of resistive elements in parallel is equal to a target resistance value that sets a predetermined gain for the second stage during the play mode,
during the play mode, the amplifier circuit is configured to generate an output signal at an output of the second stage based on the input signal, wherein, during the play mode, the second stage has a gain between the input of the second stage and the output of the second stage of a first value,
during a transition from the mute mode to the play mode, the amplifier circuit is configured to progressively increase the gain of the second stage from a second value to the first value by progressively turning on or off the plurality of switches, and
during a transition from the play mode to the mute mode, the amplifier circuit is configured to progressively decrease the gain of the second stage from the first value to the second value by progressively turning on or off the plurality of switches.

2 . The amplifier circuit of claim 1 , wherein each resistive element of the plurality of resistive elements is coupled in series with a respective switch of the plurality of switches, wherein, during the transition from the mute mode to the play mode, the amplifier circuit is configured to progressively increase the gain of the second stage from the second value to the first value by progressively turning on the plurality of switches, and wherein, during the transition from the play mode to the mute mode, the amplifier circuit is configured to progressively decrease the gain of the second stage from the first value to the second value by progressively turning off the plurality of switches.

3 . The amplifier circuit of claim 2 , wherein the plurality of resistive elements comprises a first resistor having a first resistance and a second resistor having a second resistance, wherein the first resistor is coupled in series with a first switch of the plurality of switches and the second resistor is coupled in series with a second switch of the plurality of switches, wherein the first resistance is the lowest resistance from all resistances of the resistive elements of the plurality of resistive elements, wherein the second resistance is the highest resistance from all resistances of the resistive elements of the plurality of resistive elements, and wherein, during the transition from the mute mode to the play mode, the amplifier circuit is configured to turn on the first switch firstly and the second switch lastly.

4 . The amplifier circuit of claim 2 , wherein the plurality of resistive elements comprises a first resistor having a first resistance and a second resistor having a second resistance, wherein the first resistor is coupled in series with a first switch of the plurality of switches and the second resistor is coupled in series with a second switch of the plurality of switches, wherein the first resistance is the lowest resistance from all resistances of the resistive elements of the plurality of resistive elements, wherein the second resistance is the highest resistance from all resistances of the resistive elements of the plurality of resistive elements, and wherein, during the transition from the play mode to the mute mode, the amplifier circuit is configured to turn off the second switch firstly and the first switch lastly.

5 . The amplifier circuit of claim 2 , wherein the amplifier circuit is configured to progressively turn on or off the plurality of switches based on a time in which a control voltage of each switch of the plurality of switches crosses a threshold voltage.

6 . The amplifier circuit of claim 5 , wherein the amplifier circuit is configured to progressively turn on or off the plurality of switches by sequentially applying a voltage ramp to each switch of the plurality of switches, wherein the amplifier circuit is configured to apply a first voltage ramp to a first switch of the plurality of switches, and apply a second voltage ramp to a second switch of the plurality of switches when the first voltage ramp reaches the threshold voltage.

7 . The amplifier circuit of claim 6 , wherein the first switch comprises a first metal-oxide semiconductor (MOS) transistor, and wherein the threshold voltage corresponds to a minimum gate-to-source voltage needed to create a conducting path between source and drain terminals of the first MOS transistor.

8 . The amplifier circuit of claim 5 , wherein each switch of the plurality of switches comprises a pass gate comprising an n-type transistor and a p-type transistor.

9 . The amplifier circuit of claim 8 , wherein each of the n-type transistors of the plurality of switches comprises a control terminal configured to receive a control voltage between a first supply voltage and a second supply voltage, the second supply voltage being higher than the first supply voltage, wherein the plurality of switches comprises n switches, and wherein n is a positive integer greater than 1 and smaller than the second supply voltage divided by the threshold voltage.

10 . The amplifier circuit of claim 9 , wherein n is equal to the highest integer smaller than the second supply voltage divided by the threshold voltage.

11 . The amplifier circuit of claim 8 , further comprising a control circuit configured to provide control signals to the plurality of switches, the control circuit comprising:
a first terminal configured to receive a play-mode voltage; a first current source circuit configured to generate a first current based on the play-mode voltage; a first plurality of current branches configured to generate respective first branch currents based on the first current, each current branch of the first plurality of current branches having a resistive element and an internal node coupled to the resistive element, wherein the internal node of each current branch of the first plurality of current branches is coupled to a control node of a respective transistor of the plurality of switches; a second current source circuit configured to generate a second current; and a second plurality of current branches configured to generate respective second branch currents based on the second current, each current branch of the second plurality of current branches coupled to the internal node of a respective current branch of the first plurality of current branches.

12 . The amplifier circuit of claim 11 , wherein each of the first branch currents is equal to each other, and wherein each of the second branch currents is different from each other.

13 . The amplifier circuit of claim 12 , wherein each of the second branch currents is a multiple of the second current.

14 . The amplifier circuit of claim 1 , wherein a resistive element of the plurality of resistive elements is

Assignees

• St Microelectronics Srl
• Stmicroelectronics Shenzhen R&D Co Ltd

Inventors

• Wen Jian
• Brambilla Davide Luigi
• Liu Qiyu
• Yang Mei
• Tong Shuming
• Stilgenbauer Francesco

Classifications

• H03K4/06

  having triangular shape · CPC title

• H03G3/348

  Muting in response to a mechanical action or to power supply variations, e.g. during tuning; Click removal circuits · CPC title

• H03G3/3036

  in high-frequency amplifiers or in frequency-changers (H03G3/3052, H03G3/32, H03G3/34 take precedence) · CPC title

• H03F1/303

  using a switching device (H03F1/305, H03F3/005, H03F3/38 take precedence) · CPC title

• H03F1/3211

  in differential amplifiers · CPC title