Doherty amplifier

Patent metadata

Field	Value
Publication number	US-12470176-B2
Application number	US-202318176218-A
Country	US
Kind code	B2
Filing date	Feb 28, 2023
Priority date	Mar 1, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Example embodiments relate to Doherty amplifiers. One Doherty amplifier includes a packaged main amplifier that includes a main input lead for receiving a main RF signal, a main power transistor for amplifying the main RF signal, and a main output lead for outputting the main RF signal amplified by the main power transistor. The Doherty amplifier also includes a packaged peak amplifier that includes a peak input lead assembly for receiving a peak RF signal, a first peak power transistor configured for amplifying a part of the peak RF signal, a second peak power transistor configured for amplifying a remaining part of the peak RF signal, and a peak output lead for combining the part of the peak RF signal amplified by the first peak power transistor and the remaining part of the peak RF signal amplified by the second peak power transistor into an amplified peak RF signal.

First claim

What is claimed is:

1 . A Doherty amplifier, comprising:
a packaged main amplifier comprising:
a main input lead for receiving a main RF signal;
a main power transistor configured for amplifying the main RF signal; and
a main output lead configured for outputting the main RF signal amplified by the main power transistor;
a packaged peak amplifier comprising:
a peak input lead assembly for receiving a peak RF signal;
a first peak power transistor configured for amplifying a part of the peak RF signal;
a second peak power transistor configured for amplifying a remaining part of the peak RF signal; and
a peak output lead for combining the part of the peak RF signal amplified by the first peak power transistor and the remaining part of the peak RF signal amplified by the second peak power transistor into an amplified peak RF signal; and
a Doherty combiner configured for:
combining the amplified main RF signal and the amplified peak RF signal into an RF output signal; and
outputting the RF output signal,
wherein the peak output lead comprises:
an inner edge facing the first and second peak power transistors;
an outer edge arranged opposite to the inner edge; and
a slot extending from the inner edge towards the outer edge and having a length corresponding to A times a wavelength at an operational frequency of the Doherty amplifier, wherein A lies in a range from 0.1 to 0.4,
wherein the slot divides the peak output lead in a first part, a second part, and a common part, wherein the first part is electrically connected to the first peak power transistor, wherein the second part is electrically connected to the second peak power transistor, wherein the common part is:
arranged between the outer edge and the first and second parts; and
integrally connected to the first and second parts, and
wherein the slot ensures that the part of the peak RF signal amplified by the first peak power transistor combines with the part of the peak RF signal amplified by the second peak power transistor in the common part.

2 . The Doherty amplifier according to claim 1 , further comprising:
a printed circuit board on which the packaged main amplifier and the packaged peak amplifier are mounted; and a Doherty splitter:
arranged on and/or at least partially realized in the printed circuit board; and
configured for:
receiving an RF signal; and
splitting the received RF signal into the main RF signal and the peak RF signal,

wherein the Doherty combiner is arranged on and/or at least partially realized in the printed circuit board.

3 . The Doherty amplifier according to claim 1 , wherein the main power transistor, the first peak power transistor, and the second peak power transistor are combined in a single package.

4 . The Doherty amplifier according to claim 1 ,
wherein the first peak power transistor is integrated on a first semiconductor die, and wherein the second peak power transistor is integrated on a second semiconductor die separate from the first semiconductor die.

5 . The Doherty amplifier according to claim 4 , wherein the main power transistor is integrated on a third semiconductor die separate from the first and second semiconductor die.

6 . The Doherty amplifier according to claim 1 , wherein the packaged main amplifier comprises:
an input matching network arranged in between the main input lead and the main power transistor; and/or an output matching network arranged in between the main power transistor and the main output lead.

7 . The Doherty amplifier according to claim 6 , further comprising:
a plurality of first bondwires connecting an input of the main power transistor to the main input lead either directly or via the input matching network; and a plurality of second bondwires connecting an output of the main power transistor to the main output lead either directly or via the output matching network.

8 . The Doherty amplifier according to claim 1 ,
wherein the packaged peak amplifier comprises:
a first input matching network arranged in between the peak input lead assembly and the first peak power transistor; and/or
a first output matching network arranged in between the first peak power transistor and the peak output lead, and/or
wherein the packaged peak amplifier comprises:
a second input matching network arranged in between the peak input lead assembly and the second peak power transistor; and/or
a second output matching network arranged in between the second peak power transistor and the peak output lead.

9 . The Doherty amplifier according claim 8 , further comprising:
a plurality of third bondwires connecting an input of the first peak power transistor to the peak input lead assembly either directly or via the first input matching network; a plurality of fourth bondwires connecting an input of the second peak power transistor to the peak input lead assembly either directly or via the second input matching network; a plurality of fifth bondwires connecting an output of the first peak power transistor to the first part of the peak output lead either directly or via the first output matching network; and a plurality of sixth bondwires connecting an output of the second peak power transistor to the second part of the peak output lead either directly or via the second output matching network.

10 . The Doherty amplifier according to claim 9 ,
wherein the peak input lead assembly comprises a first peak input lead and a second peak input lead spaced apart from the first peak input lead, wherein the first peak input lead is connected to the input of the first peak power transistor using the third plurality of bondwires, and wherein the second peak input lead is connected to the input of the second peak power transistor using the fourth plurality of bondwires.

11 . The Doherty amplifier according to claim 10 , further comprising
a Doherty splitter:
arranged on and/or at least partially realized in a printed circuit board;
configured for:
receiving an RF signal; and
splitting the received RF signal into the main RF signal and the peak RF signal; and

comprising:
an input for receiving the RF signal;
a main output for outputting the main RF signal; and
a peak output for outputting the peak RF signal;

a first transmission line arranged in between the peak output and the first peak input lead; and a second transmission line arranged in between the peak output and the second peak input lead, wherein the first and second transmission lines each have an electrical length that corresponds to B times a wavelength corresponding to the operational frequency of the Doherty amplifier, and wherein B lies in a range between 0.4 and 0.6.

12 . The Doherty amplifier according to claim 10 , further comprising a resistor electrically connected between the first and second peak input leads.

13 . The Doherty amplifier according to claim 1 ,
wherein the Doherty combiner comprises an impedance inverter arranged in between a or the output of the main power transistor and a combining node of the Doherty combiner, and wherein the impedance inverter is formed by a quarter wavelength transmission line corresponding to the operational frequency or an electrical equivalent thereof.

14 . The Doherty amplifier according to claim 13 ,
wherein a phase delay between a or the output of the first peak power transistor and the combining node substantially equals n 1 times 180 degrees at the operational frequency, wherein a phase delay between a or the output of the second peak power transistor and the combining node substantially equals n 2

Assignees

• Ampleon Netherlands Bv

Inventors

• Geng Zhi
• Zhu Yi

Classifications

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2200/387

  A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier · CPC title

• H03F2200/222

  A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier · CPC title