Semiconductor package electrical contact structures and related methods

Patent metadata

Field	Value
Publication number	US-12469709-B2
Application number	US-202217808338-A
Country	US
Kind code	B2
Filing date	Jun 23, 2022
Priority date	Aug 17, 2017
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

First claim

What is claimed is:

1 . A method of forming a semiconductor package, comprising:
providing a die comprising a first side and a second side; forming a first layer of a first pad and a second pad on the first side of the die; forming a second layer of the first pad and the second pad, the second layer thicker than the first layer; forming a first conductor directly on the first pad; forming a second conductor directly on the second pad; applying an organic material to the first side of the die, sidewalls of the first pad, sidewalls of the second pad, sidewalls of the first conductor, and sidewalls of the second conductor; forming a first contact layer over the first conductor; and forming a second contact layer over the second conductor; wherein a spacing between the first contact layer and the second contact layer is wider than a spacing between the second layer of the first pad and the second layer of the second pad.

2 . The method of claim 1 , wherein the first pad is a gate pad and the second pad is a source pad.

3 . The method of claim 1 , further comprising coupling a backmetal to the second side of the die.

4 . The method of claim 1 , wherein the die has a thickness of 0.1 micron to 125 microns.

5 . The method of claim 1 , wherein the first conductor is directly coupled to the first pad, the first contact layer is directly coupled to the first conductor, the second conductor is directly coupled to the second pad, and the second contact layer is directly coupled to the second conductor.

6 . The method of claim 1 , wherein a material of the second layer is the same as a material of the first layer.

7 . The method of claim 1 , wherein a material of the second layer is different from a material of the first layer.

8 . A method of forming a semiconductor package, comprising:
providing a substrate comprising a first side and a second side; forming a first pad and a second pad on the first side of the substrate; forming a first conductor on the first pad; forming a second conductor on the second pad; applying an organic material within a plurality of grooves extending partially into the first side of the substrate; forming a first contact layer over the first conductor; forming a second contact layer over the second conductor; and singulating the substrate into a plurality of die; wherein a spacing between the first contact layer and the second contact layer is wider than a spacing between the first pad and the second pad.

9 . The method of claim 8 , further comprising thinning the second side of the substrate to the plurality of grooves.

10 . The method of claim 8 , wherein the die has a thickness of 0.1 micron to 125 microns.

11 . The method of claim 8 , further comprising coupling a backmetal to the second side of the die.

12 . The method of claim 8 , wherein the organic material is directly coupled to sidewalls of the first pad, sidewalls of the second pad, sidewalls of the first conductor, and sidewalls of the second conductor.

13 . A method of forming a semiconductor package, comprising:
providing a die comprising a first side and a second side; forming a first layer of a first pad and a second pad on the first side of the die; forming a second layer of the first pad and the second pad, the second layer thicker than the first layer; forming a first conductor on the first pad; forming a second conductor on the second pad; applying a single layer of organic material to the first side of the die; forming a first contact layer over the first conductor; and forming a second contact layer over the second conductor; wherein the first conductor and the second conductor extend through corresponding openings in the single layer of organic material; wherein the first conductor comprises a perimeter entirely within a perimeter of the second layer of the first pad; wherein the second conductor comprises a perimeter entirely within a perimeter of the second layer of the second pad; and wherein a spacing between the first contact layer and the second contact layer is wider than a spacing between the second layer of the first pad and the second layer of the second pad.

14 . The method of claim 13 , wherein the first pad is a gate pad and the second pad is a source pad.

15 . The method of claim 13 , further comprising coupling a backmetal to the second side of the die.

16 . The method of claim 13 , wherein the die has a thickness of 0.1 micron to 125 microns.

17 . The method of claim 13 , wherein the organic material is directly coupled to sidewalls of the first pad, sidewalls of the second pad, sidewalls of the first conductor, and sidewalls of the second conductor.

18 . The method of claim 13 , wherein a material of the second layer is the same as a material of the first layer.

19 . The method of claim 13 , wherein a material of the second layer is different from a material of the first layer.

20 . The method of claim 13 , wherein a perimeter of the first contact layer is larger than the perimeter of the first conductor and a perimeter of the second contact layer is larger than the perimeter of the second conductor.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Carney Francis J
• Seddon Michael J
• Lin Yusheng
• Noma Takashi
• Kurose Eiji

Classifications

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title