Generating power efficient secure multiclient performance monitoring data

Patent metadata

Field	Value
Publication number	US-12468616-B2
Application number	US-202217698668-A
Country	US
Kind code	B2
Filing date	Mar 18, 2022
Priority date	Mar 18, 2022
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Various embodiments include a system for generating performance monitoring data in a computing system. The system includes a unit level counter with a set of counters, where each counter increments during each clock cycle in which a corresponding electronic signal is at a first state, such as a high or low logic level state. Periodically, the unit level counter transmits the counter values to a corresponding counter collection unit. The counter collection unit includes a set of counters that aggregates the values of the counters in multiple unit level counters. Based on certain trigger conditions, the counter collection unit transmits records to a reduction channel. The reduction channel includes a set of counters that aggregates the values of the counters in multiple counter collection units. Each virtual machine executing on the system can access a different corresponding reduction channel, providing secure performance metric data for each virtual machine.

First claim

What is claimed is:

1 . A computer-implemented method for generating performance monitoring data, the method comprising:
receiving an electronic signal representing a performance metric of a processor included in a subset of processors included in a parallel processing system; incrementing a first unit level counter associated with the performance metric during each clock cycle in which the electronic signal is at a first state; serializing a value stored in the first unit level counter to generate a serialized value; and transmitting the serialized value via one or more electronic signal paths, wherein a collection unit comprising a set of counters:
generates an aggregated counter value of the serialized value stored in the first unit level counter and other counter values,
stores the aggregated counter value into an active memory bank, and
upon receiving a trigger condition, switches the active memory bank with an idle memory bank, such that the aggregated counter value is now stored in the idle memory bank.

2 . The computer-implemented method of claim 1 , further comprising:
receiving the serialized value; deserializing the serialized value to generate a deserialized value; and adding the deserialized value to a second counter associated with the performance metric.

3 . The computer-implemented method of claim 2 , wherein the second counter comprises 28 bits.

4 . The computer-implemented method of claim 2 , further comprising:
receiving a trigger; generating a record that includes a value stored in the second counter; transmitting the record; and resetting the first unit level counter to an initial value.

5 . The computer-implemented method of claim 4 , wherein the second counter comprises 28 bits.

6 . The computer-implemented method of claim 4 , further comprising:
receiving the record; extracting the value stored in the second counter from the record; and adding the value stored in the second counter to a third counter associated with the performance metric.

7 . The computer-implemented method of claim 6 , wherein the third counter comprises 64 bits.

8 . The computer-implemented method of claim 6 , wherein the third counter is included in a set of counters associated with a virtual machine and further comprising adding the value stored in the second counter to a fourth counter associated with a device.

9 . The computer-implemented method of claim 8 , wherein the fourth counter is accessible via a secure processor.

10 . The computer-implemented method of claim 6 , further comprising storing a value stored in the third counter in a memory that is configured to store performance metrics for a hypervisor associated with the performance metric.

11 . The computer-implemented method of claim 6 , further comprising storing a value stored in the third counter in a memory that stores performance metrics for a virtual machine associated with the performance metric.

12 . The computer-implemented method of claim 6 , further comprising storing a value stored in the third counter in a memory that is configured to store performance metrics for a context associated with the performance metric.

13 . The computer-implemented method of claim 6 , further comprising:
encrypting a value stored in the third counter to generate an encrypted value; and storing the encrypted value in a memory that accessible to a central processing unit associated with the performance metric.

14 . The computer-implemented method of claim 1 , wherein the electronic signal indicates at least one of:
execution of an instruction by the processor, usage of a specified component included in the processor, occurrence of a cache miss in a cache memory, or occurrence of a cache hit in the cache memory.

15 . The computer-implemented method of claim 1 , wherein the electronic signal indicates a logic level state of a most significant bit of a second counter.

16 . The computer-implemented method of claim 1 , wherein serializing the value stored in the first unit level counter and transmitting the serialized value are performed in response to determining that a duration of time has expired.

17 . The computer-implemented method of claim 16 , wherein the first unit level counter comprises 9 bits and the duration of time represents 511 clock cycles.

18 . The computer-implemented method of claim 16 , further comprising, in response to determining that the duration of time has expired, resetting the first unit level counter to an initial value.

19 . A system comprising:
a first set of counters; a second set of counters coupled to the first set of counters and configured to:
receive an electronic signal representing a performance metric of a processor included in a subset of processors included in a parallel processing system,
increment a first counter included in the second set of counters and associated with the performance metric during each clock cycle that the electronic signal is at a first state,
serialize a value stored in the first counter to generate a serialized value, and
transmit the serialized value to a second counter included in the first set of counters via one or more electronic signal paths; and
a collection unit coupled to the first set of counters and the second set of counters and configured to:
generate an aggregated counter value of the serialized value stored in the first counter and other counter values,
store the aggregated counter value into an active memory bank, and
upon receiving a trigger condition, switch the active memory bank with an idle memory bank, such that the aggregated counter value is now stored in the idle memory bank.

20 . The system of claim 19 , wherein the collection unit is further configured to:
receive the serialized value; deserialize the serialized value to generate a deserialized value; and add the deserialized value to the second counter included in the first set of counters and associated with the performance metric.

Assignees

• Nvidia Corp

Inventors

• Vaidya Pranav
• Menezes Alan
• Sharma Siddharth
• Ouyang Jin
• Smith Gregory Paul
• Mcdonald Timothy J
• Kamalapurkar Shounak
• Ranade Abhijat
• Ogletree Thomas Melvin

Classifications

• G06F21/602 Primary

  Providing cryptographic facilities or services · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F11/3409 Primary

  for performance assessment · CPC title

• G06F21/53

  by executing in a restricted environment, e.g. sandbox or secure virtual machine · CPC title

• G06F11/3089

  Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents (software debugging using additional hardware using a specific debug interface G06F11/3656; performance evaluation by tracing or monitoring G06F11/3466) · CPC title