Digital serial read-out architecture

Patent metadata

Field	Value
Publication number	US-2022303483-A1
Application number	US-202117207712-A
Country	US
Kind code	A1
Filing date	Mar 21, 2021
Priority date	Mar 21, 2021
Publication date	Sep 22, 2022
Grant date	—

Abstract

Techniques are described for implementing read-out architectures to support high-speed serialized read-out of a large number of digital bit values, such as for high-resolution pixel conversions in CMOS image sensor applications. For example, outputs from a large number of digital data sources (e.g., counters) are coupled with transmission gates of the read-out architecture, and the transmission gates are sequentially enabled, thereby shifting in bit data from the data sources one at a time. The transmission gates are grouped into gate groups. For each gate group, embodiments seek balance total path delay across the gate groups by controlling clock and data path delays to be inversely related, and ensuring that total path delays for all gate groups are within a single clock period. Some embodiments include a partitioned bus for further gate group-level control over the path delay and data bus capacitance.

First claim

What is claimed is:

1 . A system for serialized read-out of bit data from a plurality of digital data sources, the system comprising:
an output flop configured to output a serialized output data signal responsive to a buffered data signal and an input clocking signal; a data path comprising a plurality of gate groups, each having a respective subset of a plurality of transmission gates, each transmission gate to selectively output bit data from a respective one of a plurality of digital data sources in response to assertion of a respective gate enable signal, the data path providing the data signal from the respective gate outputs of the transmission gates to the output flop by adding an amount of data path delay to the data signal to generate the buffered data signal; a clock delay block configured to generate a buffered clocking signal by adding a amount of clock path delay to the input clocking signal; and a gate selector block coupled with the clock delay block to sequentially assert each respective gate enable signal in response to the buffered clocking signal, such that a selected one of the plurality of transmission gates is enabled in each clock cycle of the input clocking signal during a shift-out routine, wherein the amount of clock path delay is different for each of the plurality of gate groups, the amount of data path delay is different for each of the plurality of gate groups.

2 . The system of claim 1 , wherein:
each transmission gate has a respective gate data input to receive the bit data from the respective one of the plurality of digital data sources, a respective gate enable input to receive the respective gate enable signal, and a respective gate output; each transmission gate is configured to provide the bit data at its respective gate data input as a data signal at its respective gate output when its respective gate enable signal is asserted; and each transmission gate is configured to provide high impedance at its respective gate output when its respective gate enable signal is de-asserted.

3 . The system of claim 1 , wherein the amount of clock path delay is inversely related to the amount of data path delay, so that a total path delay corresponding to the amount of clock path delay plus the amount of data path delay is substantially consistent across the plurality of gate groups.

4 . The system of claim 1 , wherein a total path delay corresponding to the amount of clock path delay plus the amount of data path delay is less than one clock period of the input clocking signal.

5 . The system of claim 1 , wherein:
the clock delay block comprises a plurality of clock delay buffers; and the amount of clock path delay is generated for each of the plurality of gate groups using a different respective number of the clock delay buffers.

6 . The system of claim 1 , wherein the data path comprises:
a data bus coupled with the respective gate outputs of the transmission gates to receive, in each clock cycle of the input clocking signal during the shift-out routine, the data signal from the selected one of the plurality of transmission gates enabled in the clock cycle; and a data delay block coupled between the data bus and the output flop to generate add at least a portion of the amount of data path delay to the data signal.

7 . The system of claim 6 , wherein:
the data bus contributes a first portion of the amount of data path delay added to the data signal; and the data delay block contributes a second portion of the amount of data path delay added to the data signal.

8 . The system of claim 7 , wherein:
one of the first or the second portion of the amount of data path delay is fixed across the plurality of gate groups; and the other of the first or the second portion of the amount of data path delay varies across the plurality of gate groups.

9 . The system of claim 6 , wherein:
the plurality of gate groups comprises an integer number (N) gate groups; the data bus has N bus partitions, each coupled with the respective gate outputs of the transmission gates of a respective one of the N gate groups; the data delay block is coupled with the data bus at a first bus partition; and the bus partitions are coupled with each other via one-way bus buffers, such that communication of the data signal from any of the transmission gates of a first gate group propagate to the data delay block via the first bus partition without passing through any of the one-way bus buffers, and communication of the data signal from any other of the transmission gates propagates to the data delay block via at least two of the bus partitions and at least one of the one-way bus buffers.

10 . The system of claim 1 , wherein the gate selector block comprises:
the transmission gates comprise an integer number (K) of transmission gates; an initiator flop triggered by the buffered clocking signal and configured to produce a HIGH logic level at an initiator output in a reset state and to produce a LOW logic level at the initiator output otherwise; and K gate activation flops, each triggered by the buffered clocking signal, wherein: each kth gate activation flop of the K gate activation flops has a respective kth output coupled with a respective kth one of the K transmission gates, such that a HIGH logic level at the respective kth output enables the kth one of the transmission gates; a first gate activation flop has a respective first input coupled with the initiator output; and each kth gate activation flop of the second through Kth gate activation flops has a respective kth input coupled with the (k-1)th output of the (k-1)th gate activation flop.

11 . The system of claim 10 , wherein:
the plurality of gate groups comprises N gate groups, each gate group corresponding to a respective sequence of K/N of the transmission gates, such that the respective sequence of each nth gate group begins at an associated group-start gate that is the [(n−1)*(K/N)+1]th transmission gate of the K transmission gates; the data path includes a data bus having N bus partitions; each nth bus partition is coupled with the respective gate outputs of a corresponding nth disjoint subset of the K transmission gates; the bus partitions are coupled with each other via N−1 one-way bus buffers, each bus buffer configured to provide high input impedance and high output impedance when disabled, and to provide high input impedance and low output impedance when enabled; and each nth one-way bus buffer corresponds to a respective (n+1)th gate group and is configured to be enabled responsive to assertion of the respective gate enable signal for the group-start gate associated with the (n+1)th gate group.

12 . The system of claim 1 , wherein each transmission gate is coupled with the respective gate data input via a respective input buffer.

13 . The system of claim 1 , wherein the data path comprises at least one hundred transmission gates grouped into at least four gate groups.

14 . The system of claim 1 , wherein:
each one of the plurality of digital data sources has M parallel bit outputs; the data path comprises M parallel data paths, wherein each transmission gate is a parallel set of M transmission gates, each to selectively output bit data from a respective one of the M parallel bit outputs in response to assertion of the respective gate enable signal.

15 . An analog-to-digital converter system comprising:
a plurality of digital counters, each having a respective counter output to output a respective one of a plurality of digital count values corresponding to a detected analog input voltage level

Assignees

• Shenzhen Goodix Tech Co Ltd

Inventors

• Elsayed Mohamed
• Willingham Scott D

Classifications

• H03K5/01 Primary

  Shaping pulses (discrimination against noise or interference H03K5/125) · CPC title

• H04N25/76 Primary

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/42

  by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode · CPC title

• H03K21/02

  Input circuits · CPC title

• H03K2005/00013

  Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse · CPC title