Multiple mode arithmetic circuit

Patent metadata

Field	Value
Publication number	US-12468506-B2
Application number	US-202418603800-A
Country	US
Kind code	B2
Filing date	Mar 13, 2024
Priority date	Aug 8, 2019
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

First claim

What is claimed is:

1 . A field programmable gate array (FPGA) comprising:
a floating-point multiply and accumulate (MAC) configured to operate on floating-point numbers in a first format; and bit remap logic configured to receive inputs in a second format that uses fewer bits than the first format, convert the inputs to the first format, perform sign extension on the inputs, and provide the converted inputs to the floating-point MAC.

2 . The FPGA of claim 1 , wherein the second format is selected in response to a mode selection input.

3 . The FPGA of claim 1 , further comprising:
delay registers, wherein the providing of the converted inputs to the floating-point MAC by the bit remap logic comprises storing the converted inputs in the delay registers.

4 . The FPGA of claim 1 , further comprising:
delay registers, wherein the receiving of the inputs by the bit remap logic comprises accessing the inputs from the delay registers.

5 . The FPGA of claim 1 , wherein the first format comprises a 16-bit mantissa and an 8-bit exponent.

6 . The FPGA of claim 1 , wherein the second format comprises a 10-bit mantissa and a 6-bit exponent.

7 . A non-transitory computer-readable medium containing instructions that, when executed by one or more processors, cause the one or more processors to control configuration of a field programmable gate array (FPGA) comprising:
a floating-point multiply and accumulate (MAC) configured to operate on floating-point numbers in a first format; and a bit remap logic configured to receive inputs in a second format that uses fewer bits than the first format, convert the inputs to the first format, perform sign extension on the inputs, and provide the converted inputs to the floating-point MAC.

8 . The non-transitory computer-readable medium of claim 7 , wherein the second format is selected in response to a mode selection input.

9 . The non-transitory computer-readable medium of claim 7 , further comprising:
delay registers, wherein the providing of the converted inputs to the floating-point MAC by the bit remap logic comprises storing the converted inputs in the delay registers.

10 . The non-transitory computer-readable medium of claim 7 , further comprising:
delay registers, wherein the receiving of the inputs by the bit remap logic comprises accessing the inputs from the delay registers.

11 . The non-transitory computer-readable medium of claim 7 , wherein the first format comprises a 16-bit mantissa and an 8-bit exponent.

12 . The non-transitory computer-readable medium of claim 7 , wherein the second format comprises a 10-bit mantissa and a 6-bit exponent.

13 . A method comprising:
receiving, by bit remap logic of a field programming gate array (FPGA), inputs in a second format that uses fewer bits than a first format; converting, by the bit remap logic, the inputs to the first format; performing, by the bit remap logic, sign extension on the inputs; and providing the converted inputs to a floating-point multiply and accumulate (MAC).

14 . The method of claim 13 , wherein the second format is selected in response to a mode selection input.

15 . The method of claim 13 , further comprising:
delay registers, wherein the providing of the converted inputs to the floating-point MAC by the bit remap logic comprises storing the converted inputs in the delay registers.

16 . The method of claim 13 , further comprising:
delay registers, wherein the receiving of the inputs by the bit remap logic comprises accessing the inputs from the delay registers.

17 . The method of claim 13 , wherein the first format comprises a 16-bit mantissa and an 8-bit exponent.

18 . The method of claim 13 , wherein the second format comprises a 10-bit mantissa and a 6-bit exponent.

Assignees

• Achronix Semiconductor Corp

Inventors

• Pugh Daniel
• Nijssen Raymond
• Fitton Michael Philip
• Van Der Goot Marcel

Classifications

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06F7/5324

  partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers · CPC title

• G06F2207/3824

  Accepting both fixed-point and floating-point numbers · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F7/4876 Primary

  Multiplying · CPC title