Storage power reduction in battery-operated devices

Patent metadata

Field	Value
Publication number	US-12468374-B2
Application number	US-202318230586-A
Country	US
Kind code	B2
Filing date	Aug 4, 2023
Priority date	Jun 27, 2023
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Techniques are provided for optimizing the power consumption of a data storage device included in a battery-operated device. The battery-operated device (e.g., portable devices like wearable devices, smartwatches, and mobile phones) can access certain data stored on the data storage device more frequently when the device operates on battery power as compared to when the device does not operate on battery power. Techniques are provided for identifying and classifying data into different classifications, for example, power sensitive data and non-power sensitive data. Then the device can optimize the battery power consumption of the data storage device by storing or relocating data stored at the data storage device based on the classification of the data.

First claim

What is claimed is:

1 . An apparatus comprising:
a battery configured to provide power to the apparatus during a battery power cycle and to be charged during a charging cycle; a non-volatile memory (NVM) coupled to the battery and comprising prestored data, wherein the NVM is divided into a plurality of distinct pages storing the prestored data; and one or more processors coupled to the battery and the NVM, and configured, individually or combination, to:
receive, from a host, power sensitive data (PSD) information that indicates that a first portion of the prestored data has been used more frequently than a second portion of the prestored data during the battery power cycle; and
modify storage of at least the first portion of the prestored data in the NVM based on the PSD information, wherein the one or more processors are further configured, individually or in combination, to:
determine that first data in the first portion of the prestored data is not aligned across a page boundary of the plurality of distinct pages; and
relocate the first data in the first portion of the prestored data to be within a page boundary of the plurality of distinct pages to thereby reduce a number of pages in the NVM used to store the first portion of the prestored data after the relocation.

2 . The apparatus of claim 1 , wherein the one or more processors are further configured, individually or combination, to:
determine that the first data in the first portion of the prestored data occupies less than an entirety of a first page of the NVM; and relocate the first data to a second page of the NVM, wherein the second page is occupied by second data in the first portion of the prestored data, and the second data occupies less than an entirety of the second page.

3 . The apparatus of claim 2 ,
wherein the first page and the second page are located on different dies of the NVM.

4 . The apparatus of claim 1 ,
wherein the PSD information comprises a logical block address (LBA) range for the first portion of the prestored data; and wherein the one or more processors are further configured, individually or in combination, to determine, based on the LBA range, the first portion of the prestored data.

5 . The apparatus of claim 1 , wherein the one or more processors are further configured, individually or in combination, to:
store the first portion of the prestored data in a first type of cells of the NVM; and store the second portion of the prestored data in a second type of cells of the NVM, wherein the first type of cells is configured to store more bits per cell than the second type of cells.

6 . The apparatus of claim 1 , wherein the one or more processors are further configured, individually or in combination, to cache a logical-to-physical (L2P) table with table entries for mapping the first portion of the prestored data and thereby to reduce an access time associated with retrieving the first portion of the prestored data from the NVM during the battery power cycle.

7 . The apparatus of claim 1 , wherein the one or more processors are further configured, individually or in combination, to:
relocate, during the charging cycle of the battery, data of the first data in the first portion of the prestored data to align the prestored data with the page boundary of the NVM and to thereby reduce power consumption associated with future sensing operations used to retrieve the prestored data.

8 . The apparatus of claim 7 , wherein the one or more processors are further configured, individually or in combination, to:
reduce the number of pages used to store the prestored data in the NVM during the relocation of the first data in the first portion.

9 . The apparatus of claim 1 :
wherein the NVM comprises a first type of cells and a second type of cells, the first type of cells configured to consume less power than the second type of cells during a data writing procedure; and wherein the one or more processors are further configured, individually or in combination, to:
receive an indication from the host to store data generated at the apparatus during the battery power cycle in the first type of cells; and
store the battery power cycle generated data in the first type of cells.

10 . The apparatus of claim 9 , wherein the one or more processors are further configured, individually or in combination, to free up space in the first type of cells during the charging cycle by being configured to move data from the first type of cells to the second type of cells during the charging cycle.

11 . The apparatus of claim 1 , wherein the one or more processors are further configured, individually or in combination, to communicate with the host using wireless communication.

12 . A method of operating a data storage device (DSD), the method comprising:
providing a battery configured to provide power to the DSD during a battery power cycle and to be charged during a charging cycle; providing a non-volatile memory (NVM) coupled to the battery and prestored data in the NVM, wherein the NVM is divided into a plurality of distinct pages storing the prestored data; receiving, from a host, power sensitive data (PSD) information that indicates that a first portion of the prestored data has been used more frequently than a second portion of the prestored data during the battery power cycle; and modifying storage of at least the first portion of the prestored data in the NVM based on the PSD information, wherein the modifying comprises:
determining that first data in the first portion of the prestored data is not aligned across a page boundary of the plurality of distinct pages; and
relocating the first data in the first portion of the prestored data to be within a page boundary of the plurality of distinct pages to thereby reduce a number of pages in the NVM used to store the first portion of the prestored data after the relocation.

13 . The method of claim 12 , wherein the modifying further comprises:
determining that the first data in the first portion of the prestored data occupies less than an entirety of a first page of the NVM; and relocating the first data to a second page of the NVM, wherein the second page is occupied by second data in the first portion of the prestored data, and the second data occupies less than an entirety of the second page.

14 . The method of claim 13 ,
wherein the first page and the second page are located on different dies in the NVM.

15 . The method of claim 12 ,
wherein the PSD information comprises a logical block address (LBA) range for the first portion of the prestored data, the method further comprising determining, based on the LBA range, the first portion of the prestored data.

16 . The method of claim 12 , further comprising:
storing the first portion of the prestored data in a first type of cells of the NVM; and storing the second portion of the prestored data in a second type of cells of the NVM, wherein the first type of cells is configured to store more bits per cell than the second type of cells.

17 . The method of claim 12 , further comprising:
caching a logical-to-physical (L2P) table with table entries for mapping the first portion of the prestored data and thereby to reduce an access time associated with retrieving the first portion of the prestored data from the NVM during the battery power cycle.

18 . The method of claim 12 , further comprising:
relocating, during the charging cycle of the battery, the first data in the first portion of the prestored data to align the p

Assignees

• Western Digital Tech Inc

Inventors

• Sharma Amit
• Agarwal Dinesh Kumar
• Venugopal Abhinandan

Classifications

• G06F3/0613

  in relation to throughput · CPC title

• G06F3/0638

  Organizing or formatting or addressing of data · CPC title

• G06F1/3212 Primary

  Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title