Power semiconductor device

Patent metadata

Field	Value
Publication number	US-12464749-B2
Application number	US-202118023982-A
Country	US
Kind code	B2
Filing date	Aug 19, 2021
Priority date	Sep 3, 2020
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

Disclosed is a power semiconductor device comprising a semiconductor wafer having a first main side and second main side. The semiconductor wafer comprises parallel thyristor cells, which each comprises (a) a cathode electrode and gate electrode on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type, wherein the cathode region forms a p-n junction between the first base layer and cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer. The gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts.

First claim

The invention claimed is:

1 . A power semiconductor device comprising a semiconductor wafer having a first main side and a second main side opposite to the first main side ( 1 ), the semiconductor wafer comprising a plurality of parallel thyristor cells, wherein each thyristor cell comprises in an order from the first main side to the second main side:
(a) a cathode electrode and a gate electrode arranged on the first main side; (b) a cathode layer comprising a cathode region of a first conductivity type, forming an ohmic contact with the cathode electrode; (c) a first base layer of a second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the first base layer and forms a first p-n junction between the first base layer and the cathode region; (d) a second base layer of the first conductivity type forming a second p-n junction with the first base layer; (e) an anode layer of the second conductivity type separated from the first base layer by the second base layer; wherein the gate electrode forms an ohmic contact with the first base layer, and an anode electrode is arranged on the second main side and forms an ohmic contact with the anode layer; wherein the gate electrodes of the plurality of thyristor cells form a gate design comprising multiple polygons each comprising at least four struts, wherein the cathode regions are of hexagonal shape, and the cathode layers comprise cathode short areas of the second conductivity type connecting the cathode electrodes with the first base layers, wherein the cathode short areas are of polygonal shape or circular shape or stripe shape and the cathode short areas are placed along a hexagonal gate-cathode boundary within the hexagonal cathode region.

2 . The power semiconductor device according to claim 1 , wherein the multiple polygons are connected via a central gate contact.

3 . The power semiconductor device according to claim 1 , wherein the multiple polygons are connected via a peripheral gate contact.

4 . The power semiconductor device according to claim 1 , wherein a lateral width of the struts is in a range of 0.1 mm to 1 mm, or in a range of 0.1 mm to 0.5 mm.

5 . The power semiconductor device according to claim 2 , wherein a lateral width of the struts of the polygons decreases with growing distance from the central gate contactor the peripheral gate contact.

6 . The power semiconductor device according to claim 1 , wherein the power semiconductor device is a high-power reverse blocking thyristor or a reverse conducting thyristor.

7 . The power semiconductor device according to claim 1 , comprising first cathode metal layers contacting the cathode regions and second cathode metal layers contacting the first cathode metal layers of all of the cathode regions of the plurality of thyristor cells.

8 . The power semiconductor device according to claim 7 , comprising gate-cathode insulations laterally between the gate electrodes and the first cathode metal layers on the first main side of the wafer.

9 . The power semiconductor device according to claim 8 , comprising gate insulations on the gate electrodes and on the gate-cathode insulations.

10 . The power semiconductor device according to claim 7 , wherein the first cathode metal layers form a substance-to-substance bond to the cathode regions and the second cathode metal layers form a removable connection to the first cathode metal layers which second cathode metal layers contact the first cathode metal layers of all thyristor cells as one single common disk.

11 . The power semiconductor device according to claim 1 , wherein the cathode regions comprise top sections vertically extending above a top surface of the first base layer and bottom sections within the wafer.

12 . The power semiconductor device according to claim 11 , wherein an area of the top section is smaller than an area of the bottom section.

13 . The power semiconductor device according to claim 11 comprising
gate-cathode insulations laterally between the gate electrodes and the top sections of the cathode regions and on top of the gate electrodes and
cathode electrodes on top of the gate-cathode insulations and the top sections of the cathode regions contacting the top sections of the cathode regions.

14 . The power semiconductor device according to claim 1 , wherein the plurality of thyristor cells form a honeycombed gate design comprising multiple hexagons each comprising six struts.

15 . The power semiconductor device according to claim 14 , wherein the diameter of each of the hexagons is in a range of 1 mm to 20 mm or in a range of 2 mm to 10 mm.

16 . A method for manufacturing the power semiconductor device according to claim 1 comprising the following steps:
a step of providing the wafer having a first main side;
a step of generating cathode regions within a cathode layer in the first base layer by diffusing a dopant pre-deposited at the first main side or implanting into the first main side;
a step of generating cathode short areas in the cathode layer by diffusing a dopant pre-deposited at the first main side or implanting into the first main side;
a step of forming ohmic contacts of the gate electrodes through a structured metal mask;
a step of forming gate-cathode insulations through a structured mask layer, wherein this mask layer is etched on the cathode regions;
a step of forming ohmic contacts of the cathode electrodes with the cathode regions.

17 . The power semiconductor device according to claim 3 , wherein a lateral width of the struts of the polygons decreases with growing distance from the central gate contact or the peripheral gate contact.

18 . The power semiconductor device according to claim 2 , comprising first cathode metal layers contacting the cathode regions and second cathode metal layers contacting the first cathode metal layers of all of the cathode regions of the plurality of thyristor cells.

19 . The power semiconductor device according to claim 3 , comprising first cathode metal layers contacting the cathode regions and second cathode metal layers contacting the first cathode metal layers of all of the cathode regions of the plurality of thyristor cells.

20 . The power semiconductor device according to claim 4 , comprising first cathode metal layers contacting the cathode regions and second cathode metal layers contacting the first cathode metal layers of all of the cathode regions of the plurality of thyristor cells.

Assignees

• Hitachi Energy Ltd

Inventors

• Vobecky Jan
• Vemulapati Umamaheswara

Classifications

• H10W20/484

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H10D64/291 Primary

  Gate electrodes for thyristors · CPC title

• H10D64/233

  Cathode or anode electrodes for thyristors · CPC title

• H10D62/148

  Cathode regions of thyristors · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title