Layered bottom electrode dielectric for embedded MRAM

Patent metadata

Field	Value
Publication number	US-12464731-B2
Application number	US-202117644098-A
Country	US
Kind code	B2
Filing date	Dec 14, 2021
Priority date	Dec 14, 2021
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

An MRAM device is provided. The MRAM device includes a first dielectric cap layer formed on an underlying layer, a second dielectric cap layer formed on the first dielectric cap layer, the first dielectric cap layer including a lower-κ material than that of the second dielectric cap layer. The MRAM device also includes a bottom electrode contact (BEC) formed through the first dielectric cap layer and the second dielectric cap layer, an MRAM stack formed on the BEC, and wherein the second dielectric cap layer surrounds an upper portion of the BEC.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device including a logic area and a memory area, the method comprising:
forming a first dielectric cap layer on an underlying layer in both the logic area and the memory area; forming a second dielectric cap layer on the first dielectric cap layer only in the memory area, the first dielectric cap layer including a lower-K material than that of the second dielectric cap layer; forming a bottom electrode contact (BEC) through the first dielectric cap layer and the second dielectric cap layer; forming an MRAM stack on the BEC; wherein the second dielectric cap layer surrounds an upper portion of the BEC.

2 . The method according to claim 1 , wherein the first dielectric cap layer includes carbon.

3 . The method according to claim 1 , wherein forming the second dielectric cap layer includes etching away portions of the second dielectric cap layer so that no material of the second dielectric cap layer remains in a logic area of the semiconductor device.

4 . The method according to claim 1 , wherein the second dielectric cap layer is carbon-free.

5 . The method according to claim 1 , wherein the second dielectric cap layer has a truncated conical shape having curved sidewalls.

6 . The method according to claim 1 ,
wherein a width of an upper portion of the BEC is less than a width of a lower portion of the MRAM stack.

7 . The method according to claim 1 , wherein the BEC layer has an inverted truncated conical shape.

8 . The method according to claim 1 , wherein the MRAM stack includes a bottom electrode, an MTJ stack, and a top electrode.

9 . The method according to claim 1 , further comprising forming an interlayer dielectric around the MRAM stack, and forming a top electrode contact on the MRAM stack.

10 . A semiconductor device including a logic area and a memory area the semiconductor device comprising:
a first dielectric cap layer formed on an underlying layer in both the logic area and the memory area; a second dielectric cap layer formed on the first dielectric cap layer only in the memory area, the first dielectric cap layer including a lower-k material than that of the second dielectric cap layer; a bottom electrode contact (BEC) formed through the first dielectric cap layer and the second dielectric cap layer; an MRAM stack formed on the BEC; wherein the second dielectric cap layer surrounds an upper portion of the BEC.

11 . The semiconductor device according to claim 10 , wherein the first dielectric cap layer includes carbon.

12 . The semiconductor device according to claim 10 , wherein the second dielectric cap layer surrounds an upper portion of the BEC.

13 . The semiconductor device according to claim 10 , wherein the second dielectric cap layer is carbon-free.

14 . The semiconductor device according to claim 10 , wherein the second dielectric cap layer has a truncated conical shape having curved sidewalls.

15 . The semiconductor device according to claim 10 ,
wherein a width of an upper portion of the BEC layer is less than a width of a lower portion of the MRAM stack.

16 . The semiconductor device according to claim 10 , wherein the BEC has an inverted truncated conical shape.

17 . The semiconductor device according to claim 10 , wherein the MRAM stack includes a bottom electrode, an MTJ stack, and a top electrode.

18 . The semiconductor device according to claim 10 , further comprising an interlayer dielectric formed around the MRAM stack, and forming a top electrode contact on the MRAM stack.

Assignees

• IBM

Inventors

• Dutta Ashim
• Rizzolo Michael
• Slaughter Jon
• Yang Chih-Chao
• Standaert Theodorus E

Classifications

• H10N50/80

  Constructional details · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10B61/00 Primary

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title