Three-dimensional type NAND memory device

Patent metadata

Field	Value
Publication number	US-12464722-B2
Application number	US-202217842411-A
Country	US
Kind code	B2
Filing date	Jun 16, 2022
Priority date	Mar 10, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

In one embodiment, a method of manufacturing a semiconductor device includes forming a stacked film alternately including first layers and second layers in a first direction, forming a hole extending in the first direction in the stacked film, and forming a first insulator on a side face of the stacked film in the hole. The method further includes removing the first insulator in the hole to expose a first part of the side face of the stacked film at a predetermined height in the first direction of the hole and to expose a side face of the first insulator remaining on a second part of the side face of the stacked film at the predetermined height. The method further includes forming a second insulator on the first part of the side face of the stacked film and the side face of the remaining first insulator in the hole.

First claim

The invention claimed is:

1 . A semiconductor device comprising:
a stacked film including a plurality of electrode layers separated from each other in a first direction; a first insulator provided on a first part of a side face of the stacked film at a predetermined height in the first direction; a second insulator provided on a second part of the side face of the stacked film and a side face of the first insulator at the predetermined height; a charge storage layer provided on a side face of the second insulator; a third insulator provided on a side face of the charge storage layer; and a semiconductor layer provided on a side face of the third insulator, wherein the first insulator has an outer peripheral side face having a first curvature radius and an inner peripheral side face having a second curvature radius larger than the first curvature radius.

2 . The device of claim 1 , wherein each of the first and second insulators includes silicon and oxygen.

3 . The device of claim 1 , wherein the stacked film further includes a plurality of insulators provided alternately with the plurality of electrode layers in the first direction.

4 . The device of claim 3 , wherein the first insulator is an insulator different from the plurality of insulators in the stacked film.

5 . The device of claim 1 , wherein a fourth insulator including the first and second insulators has a shape that the first insulator is projected in a convex shape from an outer peripheral side face of the second insulator.

6 . A semiconductor device comprising:
a stacked film including a plurality of electrode layers separated from each other in a first direction; a first insulator provided on a first part of a side face of the stacked film at a predetermined height in the first direction; a second insulator provided on a second part of the side face of the stacked film and a side face of the first insulator at the predetermined height; a charge storage layer provided on a side face of the second insulator; a third insulator provided on a side face of the charge storage layer; and a semiconductor layer provided on a side face of the third insulator, wherein a fourth insulator including the first and second insulators includes: a first region that includes the first and second insulators and has a first thickness; and a second region that includes only the second insulator out of the first and second insulators and has a second thickness thinner than the first thickness.

7 . The device of claim 6 , wherein each of the first and second insulators includes silicon and oxygen.

8 . The device of claim 6 , wherein the stacked film further includes a plurality of insulators provided alternately with the plurality of electrode layers in the first direction.

9 . The device of claim 8 , wherein the first insulator is an insulator different from the plurality of insulators in the stacked film.

10 . The device of claim 6 , wherein the fourth insulator has a shape that the first insulator is projected in a convex shape from an outer peripheral side face of the second insulator.

Assignees

• Kioxia Corp

Inventors

• Hamada Tatsufumi
• Mitsuno Yosuke
• Kuki Tomohiro
• Morikawa Yusuke

Classifications

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title