Semiconductor structure and forming method thereof

Patent metadata

Field	Value
Publication number	US-12463049-B2
Application number	US-202318128431-A
Country	US
Kind code	B2
Filing date	Mar 30, 2023
Priority date	Oct 16, 2020
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

Semiconductor structures and forming methods are disclosed. One form of a method includes: forming mask spacers on a base; patterning a target layer using the mask spacers as masks, to form discrete initial pattern layers, where the initial pattern layers extend along a lateral direction and grooves are formed between a longitudinal adjacent initial pattern layers; forming boundary defining grooves that penetrate through the initial pattern layers located at boundary positions of the target areas and cutting areas along the lateral direction; forming spacing layers filled into the grooves and the boundary defining grooves; and using the spacing layers located in boundary defining grooves and the spacing layers located in the grooves as stop layers along the lateral and the longitudinal directions respectively, etching the initial pattern layers located in the cutting areas, and using the remaining initial pattern layers located in the target areas as the target pattern layers.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a base, comprising target areas and cutting areas, wherein the base comprises discrete target pattern layers in the target areas, the target pattern layers extend along a lateral direction, and a direction perpendicular to the lateral direction is a longitudinal direction; cutting grooves, located on the base in the cutting areas, wherein the cutting grooves extend along the lateral direction, and the cutting grooves are connected to the target pattern layers along the lateral direction, or the cutting grooves and the target pattern layers are arranged in parallel at intervals; boundary defining grooves, located between the cutting grooves and the target pattern layers along the lateral direction; and spacing layers, filled between the adjacent target pattern layers, between side walls of the adjacent cutting grooves, and between the side walls of the cutting grooves and the target pattern layers, wherein the spacing layers are filled into the boundary defining grooves.

2 . The semiconductor structure according to claim 1 , wherein the target pattern layers are fins, channel stack layers, gate structures, pattern transferring layers or dielectric spacing layers.

3 . The semiconductor structure according to claim 1 , wherein:
the target areas are active areas, and the cutting areas are isolation areas; the target pattern layers are fins; and the semiconductor structure further comprises: residual dummy fins, located at bottoms of the cutting grooves.

4 . The semiconductor structure according to claim 1 , wherein:
the target areas are active areas, and the cutting areas are isolation areas; the target pattern layers are fins; the material of the spacing layers is a dielectric material; and the semiconductor structure further comprises: filling isolation layers, filled into the cutting grooves.

5 . The semiconductor structure according to claim 4 , wherein the material of the filling isolation layers is the same as that of the spacing layers.

6 . The semiconductor structure according to claim 1 , wherein the material of the spacing layers comprises silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxy-carbonitride, spin-on carbon, amorphous carbon, an organic dielectric layer, a silicon anti-reflective layer, a deep UV light absorbing oxide layer, a dielectric anti-reflective coating or an advanced patterning film.

7 . A semiconductor structure forming method, comprising:
providing a base, comprising a target layer, wherein the base comprises target areas for forming target pattern layers and cutting areas corresponding to cutting positions; forming discrete mask spacers on the base; patterning the target layer using the mask spacers as masks, to form discrete initial pattern layers, wherein the initial pattern layers extend along a lateral direction, a direction perpendicular to the lateral direction is a longitudinal direction, and grooves are formed between the longitudinally adjacent initial pattern layers; forming boundary defining grooves that penetrate through the initial pattern layers located at boundary positions of the target areas and the cutting areas along the lateral direction; forming spacing layers filled into the grooves and the boundary defining grooves; and using the spacing layers located in the boundary defining grooves and the spacing layers located in the grooves as stop layers along the lateral direction and the longitudinal direction respectively, etching the initial pattern layers located in the cutting areas, and using the remaining initial pattern layers located in the target areas as the target pattern layers.

8 . The semiconductor structure forming method according to claim 7 , wherein:
the step of forming mask spacers comprises:
forming discrete core layers on the base; and
forming mask spacers on side walls of the core layers; and
the semiconductor structure forming method further comprises: after the mask spacers are formed and before the target layer is patterned, removing the core layers.

9 . The semiconductor structure forming method according to claim 8 , wherein:
in the step of forming core layers, the plurality of adjacent core layers form a support core layer, and the single core layer forms a sacrificial core layer; and the semiconductor structure forming method further comprises: after the core layers are formed and before the mask spacers are formed, removing the sacrificial core layers located in the cutting areas; or in the step of forming mask spacers, the sacrificial core layers and the mask spacers located on side walls of the sacrificial core layers form sacrificial pattern layers; and after the mask spacers are formed and before the target layer is patterned, removing the sacrificial pattern layers located in the cutting areas.

10 . The semiconductor structure forming method according to claim 9 , wherein removing the sacrificial pattern layers located in the cutting areas comprises:
after the mask spacers are formed and before the core layers are removed, removing the sacrificial pattern layers located in the cutting areas; or, after the core layers are removed and before the target layer is patterned, removing the mask spacers located in the sacrificial pattern layers in the cutting areas.

11 . The semiconductor structure forming method according to claim 7 , wherein:
in the step of providing a base, the base further comprises a hard mask material layer located on the target layer; after the mask spacers are formed and before the target layer is patterned, the semiconductor structure forming method further comprises: patterning the hard mask material layer using the mask spacers as masks, to form hard mask layers; the boundary defining grooves further penetrate through the hard mask layers located at boundary positions of the target areas and the cutting areas along the lateral direction; in the step of forming the spacing layers, the spacing layers cover side walls of the hard mask layers; after the spacing layers are formed and before the initial pattern layers located in the cutting areas are etched, the semiconductor structure forming method further comprises: removing the hard mask layers located in the cutting areas, to expose tops of the initial pattern layers in the cutting areas.

12 . The semiconductor structure forming method according to claim 7 , wherein the step of forming boundary defining grooves comprises:
forming boundary defining mask layers covering the initial pattern layers, forming boundary defining openings located at boundary positions of the target areas and the cutting areas along the lateral direction in the boundary defining mask layers; etching the initial pattern layers along the boundary defining openings using the boundary defining mask layers as masks, to form the boundary defining grooves; and removing the boundary defining mask layers.

13 . The semiconductor structure forming method according to claim 12 , wherein processes for etching the initial pattern layer comprise an anisotropic dry etching process along the boundary defining openings.

14 . The semiconductor structure forming method according to claim 7 , wherein processes for forming the spacing layers comprise at least one of a flowable chemical vapor deposition process, an atomic layer deposition process or a spin-on process.

15 . The semiconductor structure forming method according to claim 7 , wherein processes for etching the initial pattern layers located in the cutting areas comprise an

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Su Bo
• Zhao Zhenyang
• Zhang Haiyang

Classifications

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/696 Primary

  Process specially adapted to improve the resolution of the mask · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title