Embeddable semiconductor-based capacitor

Patent metadata

Field	Value
Publication number	US-12462983-B2
Application number	US-202217740417-A
Country	US
Kind code	B2
Filing date	May 10, 2022
Priority date	May 14, 2021
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A semiconductor-based capacitor can include a substrate including a semiconductor material, an oxide layer formed over the substrate, a conductive layer formed over at least a portion of the oxide layer, a plurality of distinct coplanar upper terminals, and a lower terminal. The upper terminals and the lower terminal can be exposed along the top and bottom surfaces of the substrate, respectively, for embedding the capacitor in a substrate such as a circuit board. The semiconductor-based capacitor can be sufficiently miniaturized to be embeddable within a circuit board while providing superior capacitance values without compromising the integrity of the capacitor. For example, each of the upper terminals can have a maximum width and a thickness normal to the maximum width, and a ratio of the width to the thickness can be greater than about 80:1 to prevent physical damage to the capacitor from warping or cracking.

First claim

What is claimed is:

1 . An embeddable capacitor comprising:
a substrate comprising a semiconductor material; a conductive layer formed over the substrate; an intervening layer between the substrate and the conductive layer, wherein the intervening layer comprises one or more of an oxide layer and an insulator layer; a plurality of distinct coplanar upper terminals formed over the conductive layer; a lower terminal formed over a lower surface of the substrate opposite the top surface of the substrate; wherein each of the plurality of distinct coplanar upper terminals has a maximum width, a surface area, and a thickness normal to the maximum width, wherein a ratio of the maximum width to the thickness is greater than about 80:1 and a ratio of a cumulative surface area of all the upper terminals to a surface area of the substrate is in a range from about 0.6:1 to about 0.99:1.

2 . The capacitor of claim 1 , wherein the plurality of upper terminals and the lower terminal comprise at least one of copper, gold, or aluminum.

3 . The capacitor of claim 1 , wherein the thickness of each of the plurality of upper terminals is at least about 1 micron.

4 . The capacitor of claim 1 , wherein the lower terminal comprises a plurality of distinct coplanar lower terminals.

5 . The capacitor of claim 4 , wherein the plurality of lower terminals are aligned with the plurality of upper terminals with respect to the first and second directions.

6 . The capacitor of claim 1 , wherein the intervening layer comprises both the oxide layer and the insulator layer, wherein the insulator layer is formed over the oxide layer.

7 . The capacitor of claim 6 , wherein the insulator layer comprises silicon nitride.

8 . The capacitor of claim 1 , further comprising an upper protective layer formed over the conductive layer and a lower protective layer formed over the lower surface of the substrate.

9 . The capacitor of claim 8 , wherein each of the plurality of upper terminals extends through the upper protective layer in a vertical direction normal to an upper surface of the substrate.

10 . The capacitor of claim 1 , wherein each of the plurality of upper terminals are exposed along a top surface of the capacitor.

11 . The capacitor of claim 1 , wherein the lower terminal is exposed along a bottom surface of the capacitor.

12 . The capacitor of claim 1 , wherein the semiconductor material of the substrate comprises silicon.

13 . The capacitor of claim 1 , wherein the oxide layer comprises silicon oxide.

14 . The capacitor of claim 1 , wherein the capacitor comprises a capacitance value in a range from about 0.1 pF to about 1800 pF.

15 . A circuit board comprising:
a substrate that defines a mounting surface, wherein a recessed opening is provided in the mounting surface; and a capacitor comprising:
a semiconductor substrate;
a plurality of distinct coplanar upper terminals formed over an upper surface of the semiconductor substrate;
a lower terminal formed over a lower surface of the semiconductor substrate opposite the upper surface of the substrate;
wherein each of the plurality of distinct coplanar upper terminals has a maximum width, a surface area, and a thickness normal to the maximum width, wherein a ratio of the maximum width to the thickness is greater than about 80:1 and a ratio of a cumulative surface area of all the upper terminals to a surface area of the semiconductor substrate is in a range from about 0.6:1 to about 0.99:1.

16 . The circuit board of claim 15 , wherein the capacitor further comprises an oxide layer formed over the upper surface of the substrate and a conductive layer formed over the oxide layer.

17 . The circuit board of claim 16 , wherein the plurality of upper terminals are formed over the conductive layer.

18 . The circuit board of claim 16 , further comprising an insulator layer formed between the oxide layer and the conductive layer.

19 . The circuit board of claim 15 , wherein the lower terminal comprises a plurality of distinct coplanar lower terminals.

20 . A method of embedding a capacitor in a substrate comprising:
providing a substrate, wherein the substrate comprises a recessed opening in a surface of the substrate; providing a capacitor, wherein the capacitor comprises:
a semiconductor substrate;
a plurality of distinct coplanar upper terminals formed over a top surface of the semiconductor substrate;
at least one lower terminal formed over a bottom surface of the semiconductor substrate opposite the top surface of the substrate;
wherein each of the plurality of distinct coplanar upper terminals has a maximum width, a surface area, and a thickness normal to the maximum width, wherein a ratio of the maximum width to the thickness is greater than about 80:1 and a ratio of a cumulative surface area of all the upper terminals to a surface area of the substrate is in a range from about 0.6:1 to about 0.99:1;
inserting the capacitor within the recessed opening; and electrically connecting the substrate with at least one of the plurality of upper terminals of the capacitor.

Assignees

• Kyocera Avx Components Corp

Inventors

• Nelson Cory
• Borgman Jeff

Classifications

• H05K1/185

  associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards · CPC title

• H01G4/252

  the terminals being coated on the capacitive element (H01G4/232 takes precedence) · CPC title

• H01G4/005

  Electrodes · CPC title

• H01G4/1272

  Semiconductive ceramic capacitors · CPC title

• H01G4/105

  Glass dielectric · CPC title