Memory devices having sense amplifiers therein that support offset cancellation having improved sense amplifier characteristics and methods of operating same

Patent metadata

Field	Value
Publication number	US-12462867-B2
Application number	US-202318303522-A
Country	US
Kind code	B2
Filing date	Apr 19, 2023
Priority date	Aug 22, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A method of operating a memory device includes precharging a pair of true and complementary bit lines (BL/BLB) to an equivalent voltage concurrently with precharging a pair of true and complementary sense bit lines (SABL/SABLB) to the equivalent voltage, and then transferring charge associated with offset noise from BL to SABLB concurrently with transferring charge associated with the offset noise from BLB to SABL, so that a voltage difference is established between the SABL and SABLB. Next, a logic state of a memory cell connected to BI is read by transferring charge between the memory cell and BL, concurrently with equilibrating voltages on SABL and SABLB. Then, a voltage difference between SABL and SABLB is sensed and amplified in response to activating an amplifier circuit within the sense amplifier.

First claim

What is claimed is:

1 . A method of operating a memory device, comprising:
precharging a pair of true and complementary bit lines to an equivalent voltage concurrently with precharging a pair of true and complementary sense bit lines within a sense amplifier to the equivalent voltage; then transferring charge associated with offset noise from the true bit line to the complementary sense bit line concurrently with transferring charge associated with the offset noise from the complementary bit line to the true sense bit line, so that a voltage difference is established between the true sense bit line and the complementary sense bit line, wherein the memory device is configured such that a duration of said transferring charge associated with the offset noise is adjusted in response to changes in magnitude of an internal power supply voltage within the memory device; then reading a logic state of a memory cell within the memory device by transferring charge between the memory cell and the true bit line, concurrently with equilibrating voltages on the true and complementary sense bit lines; and then sensing and amplifying a voltage difference between the true and complementary sense bit lines in response to activating an amplifier circuit within the sense amplifier, said amplifier circuit electrically connected to the true and complementary sense bit lines and responsive to voltage signals developed on the true and complementary bit lines during said reading.

2 . The method of claim 1 , wherein said transferring charge comprises:
transferring charge associated with the offset noise from the true bit line to the complementary sense bit line via a first offset cancellation transistor having a first current carrying terminal electrically connected to the true bit line, a second current carrying terminal electrically connected to the complementary sense bit line, and a gate terminal responsive to an offset cancellation signal; and transferring charge associated with the offset noise from the complementary bit line to the true sense bit line via a second offset cancellation transistor having a first current carrying terminal electrically connected to the complementary bit line, a second current carrying terminal electrically connected to the true sense bit line, and a gate terminal responsive to the offset cancellation signal.

3 . The method of claim 1 , wherein the memory device is configured such that a duration of said transferring charge associated with the offset noise varies in response to changes in magnitude of an internal power supply voltage within the memory device.

4 . The method of claim 3 , wherein the memory device includes true and complementary sensing driving signal lines (LA/LAB), which are electrically connected to the amplifier circuit within the sense amplifier; and wherein said transferring charge associated with the offset noise comprises driving LA at the internal power supply voltage.

5 . The method of claim 4 , wherein said sensing and amplifying a voltage difference comprises driving LA at the internal power supply voltage.

6 . The method of claim 5 , wherein during said reading a logic state, LA and LAB are both held at a precharge voltage level having a magnitude less than the internal power supply voltage and greater than a ground reference voltage.

7 . The method of claim 1 , wherein the duration of said transferring charge associated with the offset noise varies inversely in response to changes in magnitude of an internal power supply voltage within the memory device.

8 . A memory device, comprising:
a sense amplifier including: (i) an equalization circuit, which is electrically connected to a true sense bit line and a complementary sense bit line and responsive to an equalization signal, (ii) an amplifier circuit, which is electrically connected to the true sense bit line and the complementary sense bit line and responsive to true and complementary sensing driving signals (LA/LAB), (iii) a first isolation transistor electrically connected in series between a true bit line and the true sense bit line, and a second isolation transistor electrically connected in series between a complementary bit line and the complementary sense bit line, and (iv) a first offset cancellation transistor having a first current carrying terminal electrically connected to the true bit line, a second current carrying terminal electrically connected to the complementary sense bit line, and a gate terminal responsive to an offset cancellation signal, and a second offset cancellation transistor having a first current carrying terminal electrically connected to the complementary bit line, a second current carrying terminal electrically connected to the true sense bit line, and a gate terminal responsive to the offset cancellation signal; and a control circuit configured to generate the offset cancellation signal during an operation to reduce offset noise on the true and complementary bit lines, which precedes an operation to read a logic state of a memory cell onto the true bit line, wherein the control circuit is configured such that a duration of the operation to reduce offset noise on the true and complementary bit lines is adjusted inversely in response to changes in magnitude of an internal power supply voltage within the memory device.

9 . A memory device comprising:
a memory cell array including a plurality of memory cells; a voltage detection circuit configured to detect a power supply voltage level of the memory device; a sense amplifier connected to a bit line and a complementary bit line of the memory cell array, said sense amplifier configured to perform: (i) an offset cancellation operation to reduce an offset voltage difference between the bit line and the complementary bit line, (ii) sample and detect a voltage change of the bit line, and (iii) adjust voltages of a sensing bit line and a complementary sensing bit line based on the detected voltage change; and a control circuit configured to adjust a duration of the offset cancellation operation based on a magnitude of the detected power supply voltage.

10 . The memory device of claim 9 , wherein the control circuit is configured to generate an offset cancellation signal for performing the offset cancellation operation to be activated for a first offset cancellation time, when the voltage information of the voltage detection circuit is a typical power supply voltage level defined in a specification of the memory device.

11 . The memory device of claim 10 , wherein the control circuit is configured to generate a control signal in response to a command of the memory device and generate the offset cancellation signal using delay cells that delay the control signal.

12 . The memory device of claim 11 , wherein the command comprises an active command, a read command, or a write command applied to the memory device.

13 . The memory device of claim 11 , wherein the control circuit is configured to set the offset cancellation signal to be activated for a second offset cancellation time that is longer than the first offset cancellation time, when the voltage information of the voltage detection circuit is lower than the typical power supply voltage level.

14 . The memory device of claim 13 , wherein the control circuit is configured to change the second offset cancellation time by applying a bulk bias voltage to NMOS transistors included in the delay cells, and activate the offset control signal according to the changed second offset cancellation time.

15 . The memory device of claim 9 , wherein the control circuit includes a register arra

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Seungki
• Park Jinsol
• Lim Jaeseong
• Jang Minsoo
• Hong Eunki

Classifications

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C2207/002

  Isolation gates, i.e. gates coupling bit lines to the sense amplifier · CPC title