Sense amplifier having offset cancellation

Patent metadata

Field	Value
Publication number	US-10224093-B2
Application number	US-201715697164-A
Country	US
Kind code	B2
Filing date	Sep 6, 2017
Priority date	Dec 28, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

First claim

What is claimed is:

1. A device, comprising:
an isolation transistor configured to connect a bit line to a sensing bit line in response to an isolation signal;
an offset compensation transistor configured to connect the bit line to a complementary sensing bit line in response to an offset cancellation signal; and
a sense amplifying unit configured to sense a bit line voltage of the bit line, the sense amplifying unit including a P-type metal oxide semiconductor (PMOS) transistor and an N-type metal oxide semiconductor (NMOS) transistor,
wherein the isolation transistor and the offset compensation transistor are disposed between the PMOS transistor and the NMOS transistor.

2. The device of claim 1 , wherein the PMOS transistor is a first PMOS transistor, the NMOS transistor is a first NMOS transistor, the isolation transistor is a first isolation transistor, and the offset compensation transistor is a first offset compensation transistor, the device further comprising:
a second isolation transistor configured to connect a complementary bit line to the complementary sensing bit line in response to the isolation signal; and
a second offset compensation transistor configured to connect the complementary bit line to the sensing bit line in response to the offset cancellation signal,
wherein the sense amplifying unit further includes a second PMOS transistor and a second NMOS transistor, and
wherein the second isolation transistor and the second offset compensation transistor are disposed between the second PMOS transistor and the second NMOS transistor.

3. The device of claim 2 , further comprising:
a first pattern disposed between: the first PMOS transistor on a first side of the first pattern; and the first isolation transistor and the first offset compensation transistor on a second side of the first pattern; and
a second pattern disposed between: the second PMOS transistor on a first side of the second pattern; and the second isolation transistor and the second offset compensation transistor on a second side of the second pattern.

4. The device of claim 3 , further comprising an equalizer connected between a precharge voltage line and one of the sensing bit line and the complementary sensing bit line, wherein the equalizer has a control terminal connected to an equalizing control line, and wherein the equalizer is disposed between one of the first and second PMOS transistors and one of the first and second NMOS transistors.

5. The device of claim 4 , wherein the equalizer is connected between the precharge voltage line and the sensing bit line, and wherein the equalizer is disposed between the first PMOS transistor and the first NMOS transistor.

6. The device of claim 4 , wherein the equalizer is connected between the precharge voltage line and the complementary sensing bit line, and wherein the equalizer is disposed between the second PMOS transistor and the second NMOS transistor.

7. The device of claim 1 , wherein the isolation transistor and the offset compensation transistor share a common active pattern, and each has a corresponding gate pattern.

8. A sense amplifier, comprising:
a first isolation unit configured to connect a bit line to a sensing bit line in response to an isolation signal;
a second isolation unit configured to connect a complementary bit line to a complementary sensing bit line in response to the isolation signal;
a first offset compensation unit configured to connect the bit line to the complementary sensing bit line in response to an offset cancellation signal;
a second offset compensation unit configured to connect the complementary bit line to the sensing bit line in response to the offset cancellation signal;
a pair of P-type metal oxide semiconductor (PMOS) transistors, including,
a first PMOS transistor connected between a first control line and the complementary sensing bit line, and having a control terminal connected to the sensing bit line, and
a second PMOS transistor connected between the first control line and the sensing bit line, and having a control terminal connected to the complementary sensing bit line; and

a pair of N-type metal oxide semiconductor (NMOS) transistors, including,
a first NMOS transistor connected between a second control line and the complementary sensing bit line, and having a control terminal connected to the sensing bit line, and
a second NMOS transistor connected between the second control line and the sensing bit line, and having a control terminal connected to the complementary sensing bit line,

wherein first transistors of a first pair selected from the pair of PMOS transistors and the pair NMOS transistors are disposed at opposite sides of the sense amplifier from each other, and second transistors of a second pair selected from the pair of PMOS transistors and the pair NMOS transistors are disposed in a central region of the sense amplifier between the first transistors,
wherein the first isolation unit and the first offset compensation unit are disposed between the first PMOS transistor and the first NMOS transistor, and
wherein the second isolation unit and the second offset compensation unit are disposed between the second PMOS transistor and the second NMOS transistor.

9. The sense amplifier of claim 8 , further comprising:
a first pattern disposed between: the first PMOS transistor on a first side of the first pattern; and the first isolation unit and the first offset compensation unit on a second side of the first pattern; and
a second pattern disposed between: the second PMOS transistor on a first side of the second pattern; and the second isolation unit and the second offset compensation unit on a second side of the second pattern.

10. The sense amplifier of claim 8 , further comprising an equalizer connected between a precharge voltage line and one of the sensing bit line and the complementary sensing bit line, wherein the equalizer has a control terminal connected to an equalizing control line, and wherein the equalizer is disposed between one of the first and second PMOS transistors and one of the first and second NMOS transistors.

11. The sense amplifier of claim 10 , wherein the equalizer is connected between the precharge voltage line and the sensing bit line, and wherein the equalizer is disposed between the first PMOS transistor and the first NMOS transistor.

12. The sense amplifier of claim 10 , wherein the equalizer is connected between the precharge voltage line and the complementary sensing bit line, and wherein the equalizer is disposed between the second PMOS transistor and the second NMOS transistor.

13. The sense amplifier of claim 8 , wherein the bit line is connected to a first plurality of memory cells of a first memory cell array, and the complementary bit line is connected to a second plurality of memory cells of a second memory cell array, and wherein the sense amplifier is disposed between the first memory cell array and the second memory cell array.

14. A memory device, comprising:
a first memory cell array having a bit line;
a second memory cell array having a complementary bit line; and
a sense amplifier for sensing a bit line voltage of the bit line, the sense amplifier comprising:
a first isolation unit configured to connect the bit line to a sensing bit line in response to an isolation signal;
a second isolation unit configured to connect the complementary bit line to a complementary sensing bit line in response to the isolation signal;
a first offset compensation unit configured to connect the bit line to the complementary sensing bit line in response to an offset cancellation signal;
a second o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Young-Wook
• Kwon Hyuk-Joon
• Han Sang-Keun
• Won Bok-Yeon

Classifications

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C2207/002

  Isolation gates, i.e. gates coupling bit lines to the sense amplifier · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title