Test device and test system for semiconductor devices

Patent metadata

Field	Value
Publication number	US-12461139-B2
Application number	US-202318384910-A
Country	US
Kind code	B2
Filing date	Oct 30, 2023
Priority date	Nov 24, 2022
Publication date	Nov 4, 2025
Grant date	Nov 4, 2025

Abstract

A test device includes a main board. First and second device under test (DUT) boards are disposed on the main board. First and second semiconductor devices are mounted on the first and second DUT boards, respectively. The first and second semiconductor devices are DUTs. First and second connectors are respectively disposed at a first end and a second end of the first DUT board. The first and second connectors are spaced apart from each other and respectively transmit first and second signals. The first signal forms a first electrical path along which the first signal is input to the first DUT board via the first connector. The second signal forms a second electrical path along which the second signal is output from the first DUT board and input to the second DUT board via the second connector.

First claim

What is claimed is:

1 . A test device comprising:
a main board; first and second device under test (DUT) boards disposed on the main board, wherein first and second semiconductor devices are mounted on the first and second DUT boards, respectively, the first and second semiconductor devices are DUTs; and first and second connectors respectively disposed at a first end and a second end of the first DUT board, the first and second connectors are spaced apart from each other and respectively transmit first and second signals, wherein the first signal forms a first electrical path along which the first signal is input to the first DUT board via the first connector, and the second signal forms a second electrical path along which the second signal is output from the first DUT board and input to the second DUT board via the second connector, wherein a connection board including the second connector is disposed between the second end of the first DUT board and a first end of the second DUT board, and wherein the connection board is spaced apart from the main board.

2 . The test device of claim 1 , wherein the first and second electrical paths are independent electrical paths that are not shared with each other.

3 . The test device of claim 1 , wherein the first connector is disposed between the main board and the first DUT board.

4 . The test device of claim 3 , wherein the first signal is transmitted from the main board to the first DUT board via the first connector.

5 . The test device of claim 1 , wherein the second connector is disposed between the second end of the first DUT board and the first end of the second DUT board and spaced apart from the main board.

6 . The test device of claim 5 , further comprising a third connector disposed at a second end of the second DUT board and spaced apart from the second connector, wherein the second signal is transmitted from the first DUT board to the second DUT board via the second connector, and a third signal is transmitted from the second DUT board to the main board via the third connector.

7 . The test device of claim 1 , further comprising third and fourth DUT boards spaced apart from the first and second DUT boards, wherein third and fourth semiconductor devices are mounted on the third and fourth DUT boards, respectively, the third and fourth semiconductor devices are DUTs.

8 . A test device comprising:
a main board; first and second DUT boards disposed on the main board, wherein first and second semiconductor devices are mounted on the first and second DUT boards, respectively, the first and second semiconductor devices are DUTs; a first transmission line connected to an input terminal of the first DUT board, wherein a first signal input to the first DUT board is transmitted through the first transmission line; and a second transmission line connected to an output terminal of the first DUT board, wherein a second signal output from the first DUT board and input to the second DUT board is transmitted through the second transmission line, wherein the first and second transmission lines are independent electrical lines that are not shared with each other, and wherein the second transmission line is spaced apart from the main board.

9 . The test device of claim 8 , wherein the first signal does not pass through the second transmission line, and the second signal does not pass through the first transmission line.

10 . The test device of claim 8 , wherein:
the first transmission line is disposed between the main board and the input terminal of the first DUT board; and the first signal is transmitted from the main board to the input terminal of the first DUT board via the first transmission line.

11 . The test device of claim 8 , wherein the second transmission line is disposed between the output terminal of the first DUT board and an input terminal of the second DUT board.

12 . The test device of claim 11 , wherein the second signal is transmitted from the output terminal of the first DUT board to the second DUT board via the second transmission line.

13 . The test device of claim 11 , further comprising a third transmission line connected to an output terminal of the second DUT board and spaced apart from the second transmission line, the third transmission line transmits a third signal, wherein the third signal is transmitted from the second DUT board to the main board via the third transmission line.

14 . A test system comprising:
a test facility comprising a test chamber; and a test board disposed in the test chamber and receiving power from the test facility, wherein the test board comprises: a main board; first and second DUT boards disposed on the main board, wherein first and second semiconductor devices are mounted on the first and second DUT boards, respectively, the first and second semiconductor devices are DUTs; a first transmission line connected to an input terminal of the first DUT board, wherein a first signal input to the first DUT board is transmitted through the first transmission line; and a second transmission line connected to an output terminal of the first DUT board, wherein a second signal output from the first DUT board and input to the second DUT board is transmitted through the second transmission line, wherein a transmission line is not formed between the input terminal and the output terminal in the main board.

15 . The test system of claim 14 , wherein:
the first transmission line is disposed between the main board and the input terminal of the first DUT board; and the first signal is transmitted from the main board to the input terminal of the first DUT board via the first transmission line.

16 . The test system of claim 14 , wherein:
the second transmission line is disposed between the main board and the output terminal of the first DUT board; and the second signal is transmitted from the output terminal of the first DUT board to the main board via the second transmission line.

17 . The test system of claim 14 , wherein:
the second transmission line is disposed between the output terminal of the first DUT board and an input terminal of the second DUT board, the second transmission line is spaced apart from the main board; and the second signal is transmitted from the output terminal of the first DUT board to the second DUT board via the second transmission line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Seong Seob
• Kwon Soon Il
• Park Soo Yong
• Kim Tae-Hwan

Classifications

• G01R31/2879

  related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads · CPC title

• G01R31/31715

  Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer · CPC title

• G01R31/2889

  Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence) · CPC title

• G01R31/2806 Primary

  Apparatus therefor, e.g. test stations, drivers, analysers, conveyors (G01R31/2805, G01R31/281, G01R31/2818 take precedence) · CPC title

• G01R31/31713 Primary

  Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572) · CPC title