Semiconductor device with lateral base link region

Patent metadata

Field	Value
Publication number	US-12457784-B2
Application number	US-202218066110-A
Country	US
Kind code	B2
Filing date	Dec 14, 2022
Priority date	Dec 14, 2022
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region an intrinsic base region, and a lateral base link region disposed between and in contact with each of the extrinsic base region and an intrinsic base region. The extrinsic base region, the lateral base link region, and a portion of the intrinsic base region each may be formed on a passivation layer disposed over an isolation region and a collector region of a substrate of the semiconductor device. The extrinsic base region and a first portion of the lateral base link region may be formed from polycrystalline semiconductor material. The intrinsic base region and a second portion of the lateral base link region may be formed from monocrystalline semiconductor material. The lateral base link region may be formed after formation of the extrinsic base region and the intrinsic base region.

First claim

What is claimed is:

1. A method comprising:
providing a substrate that includes an isolation region that includes dielectric material and a collector region that includes semiconductor material, and a passivation layer disposed on the substrate;
forming an extrinsic base layer on the passivation layer;
forming an intrinsic base layer over the collector region; and
forming a lateral base link region between the extrinsic base layer and the intrinsic base layer, wherein the lateral base link region is disposed on the passivation layer and directly contacts respective side surfaces of the extrinsic base layer and the intrinsic base layer, wherein the lateral base link region is separated from the collector region by at least the passivation layer, and wherein the lateral base link region is formed after forming the intrinsic base layer.

2. The method of claim 1 , wherein the extrinsic base layer comprises polycrystalline semiconductor material, the intrinsic base layer comprises monocrystalline semiconductor material, and the lateral base link region comprises a first portion that includes monocrystalline semiconductor material and a second portion that includes polycrystalline semiconductor material.

3. The method of claim 2 , wherein the first portion of the lateral base link region directly contacts the intrinsic base layer and the second portion of the lateral base link region directly contacts the extrinsic base layer.

4. The method of claim 2 , wherein the polycrystalline semiconductor material of each of the extrinsic base layer and the first portion of the lateral base link region is selected from the group consisting of polycrystalline silicon and polycrystalline silicon germanium, and wherein the monocrystalline semiconductor material of each of the intrinsic base layer and the second portion of the lateral base link region is selected from the group consisting of monocrystalline silicon and monocrystalline silicon germanium.

5. The method of claim 2 , further comprising:
forming a first dielectric stack on the extrinsic base layer;
forming an emitter window by etching a first opening in the first dielectric stack and the extrinsic base layer, wherein the first opening exposes a portion of the isolation region;
forming an oxide layer over the first dielectric stack; and
removing portions of the oxide layer via a first anisotropic etch process to form a spacer corresponding to a remaining portion of the oxide layer, wherein the spacer is disposed in contact with a side surface of the first dielectric stack and a top surface of the passivation layer.

6. The method of claim 5 , further comprising:
removing the portion of the isolation region exposed by the first opening to expose a surface of the collector region;
forming a launcher layer on the exposed surface of the collector region via selective epitaxial growth, wherein forming the intrinsic base layer over the collector region comprises forming the intrinsic base layer on the launcher layer via selective epitaxial growth; and
forming an emitter cap layer on the intrinsic base layer, wherein the emitter cap layer and the launcher layer each comprise silicon.

7. The method of claim 6 , further comprising:
forming an emitter layer on the emitter cap layer; and
forming a second dielectric stack on the emitter layer, wherein the emitter layer comprises polycrystalline semiconductor material, each of the emitter layer and the second dielectric stack are disposed at least partially in the emitter window, and a portion of the emitter layer is disposed on the spacer.

8. The method of claim 7 , further comprising:
forming an outside spacer in contact with at least a side surface and a bottom surface of the emitter layer, wherein a portion of the outside spacer comprises a portion of a first layer of the first dielectric stack.

9. The method of claim 8 , further comprising:
concurrently removing the spacer, a second layer of the first dielectric stack, and a first layer of the second dielectric stack, wherein removal of the spacer forms a second opening that is disposed between the passivation layer and the emitter layer.

10. The method of claim 9 , wherein forming the lateral base link region comprises:
forming the lateral base link region in the second opening via selective epitaxial growth of one or more semiconductor materials, respectively, on each of a side surface of the intrinsic base layer and a side surface of the extrinsic base layer.

11. A transistor device comprising:
a substrate comprising a collector region that includes semiconductor material and an isolation region that includes first dielectric material;
a dielectric layer that includes second dielectric material, wherein the dielectric layer is formed over the substrate;
a first semiconductor layer disposed on the dielectric layer overlapping the isolation region;
a second semiconductor layer disposed over the collector region, wherein at least a portion of the second semiconductor layer is disposed on the dielectric layer;
a third semiconductor layer disposed on the dielectric layer between the first semiconductor layer and the second semiconductor layer, wherein the third semiconductor layer is separated from the collector region by at least the dielectric layer; and
a fourth semiconductor layer disposed over the second semiconductor layer and the third semiconductor layer.

12. The transistor device of claim 11 , the first semiconductor layer corresponds to an extrinsic base region, the second semiconductor layer corresponds to an intrinsic base region, the third semiconductor layer corresponds to a lateral base link region, and the fourth semiconductor layer corresponds to an emitter region.

13. The transistor device of claim 11 , wherein:
the first semiconductor layer comprises semiconductor material selected from the group consisting of polycrystalline silicon and polycrystalline silicon germanium;
the second semiconductor layer comprises semiconductor material selected from the group consisting of monocrystalline silicon and monocrystalline silicon germanium;
the third semiconductor layer comprises a first portion that includes semiconductor material selected from the group consisting of monocrystalline silicon and monocrystalline silicon germanium; and
the third semiconductor layer comprises a second portion that includes semiconductor material selected from the group consisting of polycrystalline silicon and polycrystalline silicon germanium.

14. The transistor device of claim 11 , further comprising:
a fifth semiconductor layer disposed between the collector region and the second semiconductor layer; and
a sixth semiconductor layer disposed between the second semiconductor layer and the fourth semiconductor layer.

15. The transistor device of claim 14 , wherein the fifth semiconductor layer corresponds to a launcher layer formed from silicon, and the sixth semiconductor layer corresponds to an emitter cap layer formed from silicon.

16. The transistor device of claim 14 , further comprising:
an inside spacer disposed between the fourth semiconductor layer and the sixth semiconductor layer, the inside spacer comprising one or more layers of one or more dielectric materials; and
an outside spacer disposed in contact with a side surface of the fourth semiconductor layer and a bottom surface of the fourth semiconductor layer.

17. The transistor device of claim 16 , further comprising:
an oxide layer disposed on the bottom surface of the fourth semiconductor layer between the inside spacer and the outside spacer.

Assignees

• Nxp Bv

Inventors

• John Jay Paul
• Kirchgessner James Albert

Classifications

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D62/136

  of heterojunction BJTs  (vertical heterojunction BJTs having one or more non-monocrystalline Group IV elements H10D10/861) · CPC title

• H10D10/861

  having an emitter region comprising one or more non-monocrystalline elements of Group IV, e.g. amorphous silicon · CPC title

• H10D10/021

  of heterojunction BJTs [HBT] · CPC title

• H10D10/891

  comprising lattice-mismatched active layers, e.g. SiGe strained-layer transistors · CPC title