Gate cut structures

Patent metadata

Field	Value
Publication number	US-12457779-B2
Application number	US-202217687045-A
Country	US
Kind code	B2
Filing date	Mar 4, 2022
Priority date	Mar 4, 2022
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

Techniques are provided herein to form semiconductor devices having gate cut structures. Adjacent semiconductor devices having semiconductor regions (e.g., fins or nanoribbons) extending in a first direction have a gate structure that extends over the semiconductor regions in a second direction and are separated by a gate cut structure extending in the first direction and interrupting the gate structure. The gate cut structure further extends between adjacent source or drain regions (corresponding to the adjacent semiconductor devices). A dielectric liner on at least a sidewall and/or top surface of the source or drain regions and also extends up a sidewall surface of the gate cut structure. In some cases, the gate structure includes a gate dielectric present on the semiconductor regions, but not present on the gate cut structure. A contact may pass through the liner and at least partially land on a source or drain region.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a semiconductor device having a semiconductor region extending between a first source or drain region and a second source or drain region; a gate layer comprising a conductive material, the gate layer extending over the semiconductor region; a gate cut structure comprising a dielectric material, the gate cut structure being adjacent to the semiconductor region such that the gate cut structure interrupts the gate layer, the gate cut structure further extending adjacent to the first source or drain region; a dielectric liner on at least a sidewall and/or top surface of the first source or drain region and also on at least a portion of a sidewall of the gate cut structure adjacent to the first source or drain region; and a gate dielectric between the gate layer and the semiconductor region, wherein the gate dielectric is not present on a sidewall of the gate cut structure.

2 . The integrated circuit of claim 1 , wherein the semiconductor region comprises a plurality of semiconductor nanoribbons.

3 . The integrated circuit of claim 1 , wherein the dielectric material of the gate cut structure is a first dielectric material and the dielectric liner comprises a second dielectric material that is elementally different than the first dielectric material.

4 . The integrated circuit of claim 1 , wherein the gate cut structure is a first gate cut structure adjacent to a first side of the first source or drain region and the integrated circuit further comprises a second gate cut structure adjacent to an opposite second side of the first source or drain region.

5 . The integrated circuit of claim 1 , wherein the dielectric liner is on at least one sidewall of the first source or drain region.

6 . The integrated circuit of claim 5 , wherein the dielectric liner continues along the at least one sidewall of the first source or drain region and along the sidewall of the gate cut structure without any discontinuities between the first source or drain region and the gate cut structure.

7 . A printed circuit board comprising the integrated circuit of claim 1 .

8 . The integrated circuit of claim 1 , further comprising a contact at least partially on an upper surface of the first source or drain region.

9 . An electronic device, comprising:
a chip package comprising one or more dies, at least one of the one or more dies comprising a semiconductor device having a semiconductor region extending between a first source or drain region and a second source or drain region; a gate layer comprising a conductive material, the gate layer extending over the semiconductor region; a gate cut structure comprising a dielectric material, the gate cut structure being adjacent to the semiconductor region such that the gate cut structure interrupts the gate layer, the gate cut structure further extending adjacent to the first source or drain region; a dielectric liner on at least a sidewall and/or top surface of the first source or drain region and on at least a portion of a sidewall of the gate cut structure adjacent to the first source or drain region; and a gate dielectric between the gate layer and the semiconductor region, wherein the gate dielectric is not present on a sidewall of the gate cut structure.

10 . The electronic device of claim 9 , wherein the semiconductor region comprises a plurality of semiconductor nanoribbons.

11 . The electronic device of claim 9 , wherein the dielectric material of the gate cut structure is a first dielectric material and the dielectric liner comprises a second dielectric material that is elementally different than the first dielectric material.

12 . The electronic device of claim 9 , wherein the dielectric liner is on at least one sidewall of the first source or drain region.

13 . The electronic device of claim 12 , wherein the dielectric liner continues along the at least one sidewall of the first source or drain region and along the sidewall of the gate cut structure without any discontinuities between the first source or drain region and the gate cut structure.

14 . The electronic device of claim 9 , wherein the at least one of the one or more dies further comprises a contact at least partially on an upper surface of the first source or drain region.

15 . An integrated circuit comprising:
a semiconductor device having a semiconductor region extending between a first source or drain region and a second source or drain region; a gate layer comprising a conductive material, the gate layer extending over the semiconductor region; a gate cut structure comprising a dielectric material, the gate cut structure being adjacent to the semiconductor region such that the gate cut structure interrupts the gate layer, the gate cut structure further extending adjacent to the first source or drain region; a dielectric liner on at least a sidewall and/or top surface of the first source or drain region; and a gate dielectric between the gate layer and the semiconductor region, wherein the gate dielectric is not present on a sidewall of the gate cut structure, and wherein the first source or drain region contacts the adjacent gate cut structure at a given contact point and wherein the dielectric liner is further on a sidewall portion of the gate cut structure that is only above the contact point.

16 . The integrated circuit of claim 15 , wherein the semiconductor region comprises a plurality of semiconductor nanoribbons.

17 . The integrated circuit of claim 15 , wherein the dielectric material of the gate cut structure is a first dielectric material and the dielectric liner comprises a second dielectric material that is elementally different than the first dielectric material.

18 . The integrated circuit of claim 15 , wherein the dielectric liner is on at least one sidewall of the first source or drain region.

19 . The integrated circuit of claim 18 , wherein the dielectric liner continues along the at least one sidewall of the first source or drain region and along the sidewall of the gate cut structure without any discontinuities between the first source or drain region and the gate cut structure.

20 . The integrated circuit of claim 15 , further comprising a contact at least partially on an upper surface of the first source or drain region.

Assignees

• Intel Corp

Inventors

• Guler Leonard P
• Liu Shengsi
• Joachim Robert
• Hasan Mohammad
• Ghani Tahir

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title