Semiconductor device and data storage system including the same

Patent metadata

Field	Value
Publication number	US-12457747-B2
Application number	US-202217715508-A
Country	US
Kind code	B2
Filing date	Apr 7, 2022
Priority date	Jul 2, 2021
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

A semiconductor device includes a first structure having first and second memory regions, an extension region therebetween, and word lines; and a second structure having a circuit region overlapping the extension region. The word lines include first and second common word lines at different levels, and first and second intermediate individual word lines at a same level and spaced apart. Each of the first and second common word lines are in the first and second memory regions and the extension region. The first intermediate individual word line is in the first memory region and extends into the extension region at a level between the first and second common word lines. The second intermediate individual word line is in the second memory region and extends into the extension region. The circuit region includes pass transistors connected to the word lines. A pass transistor overlaps the word lines in the extension region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first structure having a first memory region, a second memory region, and an extension region between the first memory region and the second memory regions, the first structure including word lines spaced apart from each other; and
a second structure having a circuit region overlapping the extension region in a vertical direction perpendicular to an upper surface of the second structure,
wherein:
the word lines include a first common word line and a second common word lines disposed at different height levels relative to the upper surface of the second structure, and a first intermediate individual word line and a second intermediate individual word lines disposed at a first same height level relative to the upper surface of the second structure and spaced apart from each other,
each of the first common word line and the second common word line is disposed in the first memory region, the extension region, and the second memory region,
the first intermediate individual word line is disposed in the first memory region and extends into the extension region, wherein the first intermediate individual word line is disposed at a height level that is between the different height levels of the first common word line and the second common word line,
the second intermediate individual word line is disposed in the second memory region and extends into the extension region,
the circuit region includes pass transistors electrically connected to the word lines,
the pass transistors include common transistors and individual transistors, and
at least one of the common transistors and at least one of the individual transistors overlap the word lines in the extension region.

2. The semiconductor device as claimed in claim 1 , wherein:
each of the individual transistors includes a first impurity region, a second impurity region, a first channel region between the first impurity region and the second impurity regions, and a first gate on the first channel region, and
each of the common transistors includes a third impurity region and a fourth impurity region, a second channel region between the third impurity region and the fourth impurity regions, and a second gate on the second channel region.

3. The semiconductor device as claimed in claim 2 , wherein:
the first channel region has a first channel width,
the second channel region has a second channel width, and
the second channel width is greater than the first channel width.

4. The semiconductor device as claimed in claim 1 , wherein:
the first common word line and the second common word lines are electrically connected to the common transistors, respectively, and
the first intermediate individual word line and the second intermediate individual word lines are electrically connected to the individual transistors, respectively.

5. The semiconductor device as claimed in claim 1 , wherein:
the word lines further include a first upper individual word line and a second upper individual word line, wherein the first upper individual word line and the second upper individual word line are disposed at a second same height level relative to the upper surface of the second structure and are spaced apart from each other, and are disposed at a height level higher than the second common word line, the second same height level being different from the first same height level,
the first upper individual word line is disposed in the first memory region and extends into the extension region, and
the second upper individual word line is disposed in the second memory region and extends into the extension region.

6. The semiconductor device as claimed in claim 5 , wherein the first structure further includes:
a first vertical memory structure penetrating through the first common word line, the first intermediate individual word line, the second common word line, and the first upper individual word line in the first memory region; and
a second vertical memory structure penetrating through the first common word line, the second intermediate individual word line, the second common word line, and the second upper individual word line in the second memory region.

7. The semiconductor device as claimed in claim 6 , further comprising:
a first bit line disposed on the first vertical memory structure and electrically connected to the first vertical memory structure;
a second bit line disposed on the second vertical memory structure and electrically connected to the second vertical memory structure;
a first common contact plug contacting the first common word line in the extension region;
a second common contact plug contacting the second common word line in the extension region;
a first intermediate individual contact plug contacting the first intermediate individual word line in the extension region;
a second intermediate individual contact plug contacting the second intermediate individual word line in the extension region;
a first upper individual contact plug contacting the first upper individual word line in the extension region; and
a second upper individual contact plug contacting the second upper individual word line in the extension region.

8. The semiconductor device as claimed in claim 7 , wherein:
a distance between the first vertical memory structure and the first common contact plug is greater than a distance between the first vertical memory structure and the first intermediate individual contact plug, and
a distance between the first vertical memory structure and the second common contact plug is smaller than the distance between the first vertical memory structure and the first intermediate individual contact plug.

9. The semiconductor device as claimed in claim 7 , wherein:
a distance between the first vertical memory structure and the first common contact plug is greater than a distance between the first vertical memory structure and the first intermediate individual contact plug,
a distance between the first vertical memory structure and the second common contact plug is greater than the distance between the first vertical memory structure and the first intermediate individual contact plug, and
the distance between the first vertical memory structure and the first common contact plug is greater than the distance between the first vertical memory structure and the second common contact plug.

10. The semiconductor device as claimed in claim 1 , wherein the first structure is disposed on the second structure.

11. The semiconductor device as claimed in claim 1 , wherein the first structure is disposed below the second structure.

12. A semiconductor device, comprising:
a first structure having a first memory region, a second memory region, and an extension region between the first and second memory regions; and
a second structure including a circuit region overlapping the extension region in a vertical direction perpendicular to an upper surface of the second structure, wherein:
the first structure includes:
first lower common gate electrodes disposed in the first memory region and the second memory regions and the extension region, and spaced apart from each other in the vertical direction;
first intermediate individual gate electrodes disposed in the first memory region, extending into the extension region, disposed at a first higher level, relative to the upper surface of the second structure, than the first lower common gate electrodes, and spaced apart from each other in the vertical direction;
second intermediate individual gate electrodes disposed in the second memory region, extending into the extension region, disposed at the same he

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Hyemin
• Yang Woosung
• Sung Sukkang
• Lee Ahreum

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10B43/40 Primary

  characterised by the peripheral circuit region · CPC title