Pixel and display device

Patent metadata

Field	Value
Publication number	US-12456402-B2
Application number	US-202418653941-A
Country	US
Kind code	B2
Filing date	May 2, 2024
Priority date	Jun 28, 2018
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

The present embodiments disclose a display device. A display device according to an embodiment of the present disclosure may include an array of pixels, each pixel connected to a respective luminous element. The array of pixels comprises a first pixel comprising a first memory to configured to store image data to drive a first luminous element; and at least one pixel directly adjacent to the first pixel, each of the at least one pixel comparing a second memory electrically connected to the first memory, wherein the second memory is configured to receive the n-bit data from the first memory.

First claim

The invention claimed is:

1. A display including an array of pixels, each pixel connected to a respective set of luminous elements, the array of pixels comprising:
a first pixel comprising:
a first memory configured to store first image data to drive a first set of luminous elements; and

at least one pixel adjacent to the first pixel, wherein each of the at least one pixel comprises:
a second memory configured to store a second image data to drive a second set of luminous elements and electrically connected to the first memory, wherein the second memory is configured to receive the first image data from the first memory and store the first image data as the second image data to drive the second set of luminous elements.

2. The display according to claim 1 , wherein each of the first and second memories include shift registers.

3. The display according to claim 1 , wherein the at least one pixel is adjacent to the first pixel on the top, bottom, left or right.

4. The display according to claim 1 , wherein each pixel includes a pixel drive circuit comprising:
an input multiplexer equipped with a plurality of input terminals configured to receive image data from an adjacent pixel; and
an output multiplexer equipped with a plurality of output terminals configured to transmit the image data to an adjacent pixel.

5. The display according to claim 4 , wherein the at least one pixel comprising: a second pixel directly adjacent to the first pixel in a up direction; a third pixel directly adjacent to the first pixel in a down direction; a fourth pixel directly adjacent to the first pixel in a right direction; and a fifth pixel directly adjacent to the first pixel in a left direction.

6. The display according to claim 5 , further comprising:
a controller connected to an input multiplexer and output multiplexer of the first pixel through a control signal bus, wherein the controller is configured to instruct which direction to shift the first image data.

7. The display according to claim 1 , further comprising:
a clock generator configured to supply a clock signal to the first and second memories.

8. The display according to claim 7 , wherein
the first memory is configured to move the first image data by one bit at one clock signal to one of the at least one pixel adjacent.

Assignees

• Sapien Semiconductors Inc

Inventors

• Jung Jun Young
• Jang Jin Woong

Classifications

• G09G2340/0464

  Positioning · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0871

  with level shifting · CPC title

• G09G2300/0814

  used for selection purposes, e.g. logical AND for partial update · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title