Semiconductor device

Patent metadata

Field	Value
Publication number	US-12453166-B2
Application number	US-202218084445-A
Country	US
Kind code	B2
Filing date	Dec 19, 2022
Priority date	May 20, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, and a gate electrode. The first semiconductor region is located on the first electrode. The second semiconductor region is located on the first semiconductor region, and includes a first contact region. The third semiconductor region is located on a portion of the second semiconductor region. The third semiconductor region includes a second contact region. A concentration of a first element in the second contact region is less than a concentration of the first element in the first contact region. The first element is at least one selected from the group consisting of platinum group elements and gold. The gate electrode faces the second semiconductor region via a gate insulating layer. The second electrode is located on the second and third semiconductor regions and contacts the first and second contact regions.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first electrode;
a first semiconductor region located on the first electrode, the first semiconductor region being of an n-type;
a second semiconductor region located on the first semiconductor region, the second semiconductor region being of a p-type and including a first contact region;
a third semiconductor region located on a portion of the second semiconductor region, the third semiconductor region being of the n-type and including a second contact region, a concentration of a first element in the second contact region being less than a concentration of the first element in the first contact region, the first element being at least one selected from the group consisting of platinum group elements and gold;
a gate electrode facing the second semiconductor region via a gate insulating layer; and
a second electrode located on the second and third semiconductor regions, the second electrode contacting the first and second contact regions, wherein:
the gate electrode faces the second semiconductor region via the gate insulating layer in a second direction perpendicular to a first direction, and
the first direction is from the first electrode toward the first semiconductor region; and

wherein the first semiconductor region includes:
a first region facing the gate electrode via the gate insulating layer in the second direction; and
a second region positioned lower than the first region, and

wherein a concentration of the first element in the first region is greater than a concentration of the first element in the second region.

2. The device according to claim 1 , wherein
the first contact region includes a silicide of the first element.

3. The device according to claim 2 , wherein
the second electrode includes a metal, and
the second contact region includes a silicide of the metal.

4. The device according to claim 1 , further comprising:
a conductive part located in the first semiconductor region with an insulating layer interposed.

5. The device according to claim 1 , wherein
the gate electrode faces the second semiconductor region via the gate insulating layer in a first direction, and
the first direction is from the first electrode toward the first semiconductor region.

6. The device according to claim 1 , wherein
the first element is platinum.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Kikuchi Kenji
• Kachi Tsuyoshi
• Baba Shotaro

Classifications

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title

• H10D30/0295

  using recessing of the source electrodes · CPC title