Memory circuitry and method used in forming memory circuitry

Patent metadata

Field	Value
Publication number	US-12453093-B2
Application number	US-202217948521-A
Country	US
Kind code	B2
Filing date	Sep 20, 2022
Priority date	Sep 20, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. The channel-material strings directly electrically couple to conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-blocks. The laterally-outer insulative lining has its lowest surface between a top and a bottom of the lowest conductive tier. The laterally-outer insulative lining has its highest surface at or below a lowest surface of the next-lowest conductive tier. Laterally-inner insulating material extends longitudinally-along the immediately-laterally-adjacent memory blocks laterally-inward of the laterally-outer insulative lining. An interface is between the laterally-outer insulative lining and the laterally-inner insulating material. Methods are also disclosed.

First claim

The invention claimed is:

1. A method used in forming memory circuitry, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier, the stack comprising laterally-spaced memory-block regions;
forming channel-material strings that extend through the first and second tiers in the memory-block regions, the channel-material strings directly electrically coupling to conductor material of the conductor tier at least in a finished-circuitry construction; and
forming intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions, the intervening material in the finished-circuitry construction comprising:
a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-block regions, the laterally-outer insulative lining having its lowest surface between a top and a bottom of the lowest first tier in the finished-circuitry construction, the laterally-outer insulative lining having its highest surface at or below a lowest surface of the next-lowest first tier in the finished-circuitry construction;
laterally-inner insulating material extending the immediately-laterally-adjacent longitudinally-along memory-block regions laterally-inward of the laterally-outer insulative lining; and
an interface between the laterally-outer insulative lining and the laterally-inner insulating material.

2. The method of claim 1 wherein the highest surface of the laterally-outer insulative lining is above a lowest surface of the lowest second tier in the finished-circuitry construction.

3. The method of claim 1 wherein the highest surface of the laterally-outer insulative lining is at the lowest surface of the next-lowest first tier in the finished-circuitry construction.

4. The method of claim 3 wherein the laterally-outer insulative lining is homogenous.

5. The method of claim 1 wherein the laterally-outer insulative lining and the laterally-inner insulating material are of different compositions relative one another.

6. The method of claim 1 wherein the laterally-outer insulative lining and the laterally-inner insulating material are of the same composition relative one another.

7. A method used in forming memory circuitry, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier, the stack comprising horizontally-elongated trenches extending through the first tiers and the second tiers and that are individually between immediately-laterally-adjacent memory-block regions;
forming channel-material strings that extend through the first and second tiers in the memory-block regions;
forming an etch-stop lining in the horizontally-elongated trenches that extends longitudinally-along the immediately-laterally-adjacent memory-block regions, the etch-stop lining comprising a doped silicon nitride having dopant therein at a total atomic concentration of 0.05 to 35 atomic percent;
through the horizontally-elongated trenches, etching material in the lowest first tier that is laterally-outward of the channel material of the channel-material strings selectively relative to exposed portions of the doped silicon nitride of the etch-stop lining; and
after the etching and through the horizontally-elongated trenches, forming conducting material in the lowest first tier that directly electrically couples together the channel material of the channel-material strings and conductor material of the conductor tier.

8. The method of claim 7 wherein total dopant atomic concentration in the doped silicon nitride is 3 to 14 atomic percent.

9. The method of claim 7 wherein the dopant comprises at least one of carbon, boron, phosphorus, and an elemental-form metal.

10. The method of claim 9 wherein the dopant comprises carbon.

11. The method of claim 9 wherein the dopant comprises boron.

12. The method of claim 9 wherein the dopant comprises phosphorus.

13. The method of claim 9 wherein the dopant comprises elemental-form metal.

14. The method of claim 7 comprising removing all of the etch-stop lining comprising the doped silicon nitride after the etching.

15. The method of claim 14 wherein the removing all of the etch-stop lining comprises removing the dopant from the doped silicon nitride to form a silicon oxynitride-comprising lining in the horizontally-elongated trenches.

16. The method of claim 15 comprising etching all of the silicon oxynitride-comprising lining from the horizontally-elongated trenches.

17. The method of claim 7 comprising forming the conducting material laterally-over the etch-stop lining comprising the doped silicon nitride.

18. The method of claim 17 comprising removing all of the etch-stop lining comprising the doped silicon nitride after forming the conducting material laterally-over the etch-stop lining comprising the doped silicon nitride.

19. The method of claim 7 comprising converting only a bottom portion of the doped silicon nitride to silicon oxynitride to leave doped silicon nitride there-above.

20. The method of claim 7 comprising forming a laterally-outer insulative lining of different composition from that of the doped silicon nitride and to extend longitudinally-along the immediately-laterally-adjacent memory-block regions, the etch-stop lining being formed after and laterally-inward of the laterally-outer insulative lining.

21. The method of claim 20 wherein the laterally-outer insulative lining has its lowest surface in a finished-circuitry construction between a top and a bottom of the lowest first tier, the laterally-outer insulative lining having its highest surface at or below a lowest surface of the next-lowest first tier in the finished-circuitry construction.

22. The method of claim 20 wherein the highest surface of the laterally-outer insulative lining is above a lowest surface of the lowest second tier in the finished-circuitry construction.

23. The method of claim 20 wherein the highest surface of the laterally-outer insulative lining is at the lowest surface of the next-lowest first tier in the finished-circuitry construction.

24. The method of claim 23 wherein the laterally-outer insulative lining is homogenous.

25. A memory array comprising strings of memory cells, comprising:
laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier, strings of memory cells comprising channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks, the channel-material strings directly electrically coupling to conductor material of the conductor tier; and
intervening material laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks, the intervening material comprising:
a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-blocks, the laterally-outer insulative lining having its lowest surface between a top and a bottom of the lowest conductive tier, the laterally-outer insulative lining having its highest surface at or below a lowest surface of the next-lowest conductive tier;
laterally-inner insulating material extending longitudinally-along the immediately-laterally-adjacent memory blocks laterally-inward of the laterally-outer insulative linin

Assignees

• Micron Technology Inc

Inventors

• Li Andrew
• Gupta Sidhartha
• Saxler Adam W

Classifications

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title