Image sensor and operating method thereof

Patent metadata

Field	Value
Publication number	US-12452558-B2
Application number	US-202318460587-A
Country	US
Kind code	B2
Filing date	Sep 4, 2023
Priority date	Mar 22, 2023
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

Disclosed is an image sensor including a plurality of column lines, a plurality of pixels coupled to the plurality of column lines, and configured to output a plurality of pixel signals to the plurality of column lines in response to first control signals, and a plurality of memory cells coupled to the plurality of column lines, and configured to output a plurality of convolution signals, in which a plurality of data signals are reflected in the plurality of pixel signals, to the plurality of column lines in response to second control signals.

First claim

What is claimed is:

1. An image sensor comprising:
a plurality of column lines;
a plurality of pixels coupled to the plurality of column lines, and configured to output a plurality of pixel signals to the plurality of column lines in response to first control signals; and
a plurality of memory cells coupled to the plurality of column lines, and configured to output a plurality of convolution signals, in which a plurality of data signals are reflected in the plurality of pixel signals, to the plurality of column lines in response to second control signals.

2. The image sensor of claim 1 , further comprising:
a signal converter coupled to the plurality of column lines, and configured to convert the plurality of pixel signals into a plurality of first digital signals and convert the plurality of convolution signals into a plurality of second digital signals; and
a row controller configured to generate the first control signals and generate the second control signals based on the plurality of first digital signals.

3. The image sensor of claim 1 , wherein the plurality of memory cells store the plurality of data signals.

4. The image sensor of claim 3 , wherein each of the plurality of data signals includes a weight.

5. The image sensor of claim 1 , wherein each of the plurality of memory cells includes a switch element and a resistive memory element.

6. The image sensor of claim 1 , wherein neighboring first and second pixels among the plurality of pixels are configured in first and second regions, respectively, and a first memory cell adjacent to the first and second pixels among the plurality of memory cells is configured in a third region that is disposed to partially overlap with the first and second regions.

7. The image sensor of claim 1 , wherein the plurality of memory cells write the plurality of data signals in response to the second control signals in a test mode.

8. An image sensor comprising:
a first die including a pixel array and a memory cell array; and
a second die stacked at a top or bottom of the first die, and configured to generate first control signals for controlling the pixel array and second control signals for controlling the memory cell array, and process a plurality of pixel signals generated by the pixel array and a plurality of convolution signals generated by the memory cell array; and
wherein:
the pixel array and the memory cell array share a plurality of column lines,
the pixel array outputs the plurality of pixel signals to the plurality of column lines, and
the memory cell array outputs the plurality of convolution signals to the plurality of column lines.

9. The image sensor of claim 8 , wherein the second die generates the second control signals based on a plurality of first digital signals corresponding to the plurality of pixel signals.

10. The image sensor of claim 8 , wherein each of the first control signals, the second control signals, the plurality of pixel signals and the plurality of convolution signals is transmitted through a through-silicon via or hybrid bonding.

11. The image sensor of claim 8 , wherein the first die includes:
the plurality of column lines;
the pixel array coupled to the plurality of column lines, and configured to output the plurality of pixel signals to the plurality of column lines in response to the first control signals; and
the memory cell array coupled to the plurality of column lines, and configured to output the plurality of convolution signals, in which a plurality of data signals are reflected in the plurality of pixel signals, to the plurality of column lines in response to the second control signals.

12. The image sensor of claim 11 , wherein the memory cell array includes a plurality of memory cells for storing the plurality of data signals.

13. The image sensor of claim 12 , wherein each of the plurality of memory cells includes a switch element and a resistive memory element.

14. The image sensor of claim 11 , wherein the memory cell array writes the plurality of data signals in response to the second control signals in a test mode.

15. The image sensor of claim 11 , wherein the second die includes:
a signal converter coupled to the plurality of column lines, and configured to convert the plurality of pixel signals into a plurality of first digital signals and convert the plurality of convolution signals into a plurality of second digital signals; and
a row controller configured to generate the first control signals and generating the second control signals based on the plurality of first digital signals.

16. An operation method of an image sensor, the operation method comprising:
reading out a plurality of pixel signals in response to first control signals;
converting the plurality of pixel signals into a plurality of first digital signals;
generating second control signals based on the plurality of first digital signals;
generating a plurality of convolution signals, in which a plurality of weights are reflected in the plurality of pixel signals, in response to the second control signals; and
converting the plurality of convolution signals into a plurality of second digital signals,
wherein the generating of the plurality of convolution signals comprises generating respective convolution signals based on signals outputted from memory cells arranged in at least one column.

17. The operation method of claim 16 , wherein the generating of the plurality of convolution signals comprises performing matrix multiplication on the signals outputted from the memory cells arranged in the at least one column to generate the respective convolution signals.

18. The operation method of claim 16 , wherein each of the plurality of convolution signals is an analog signal.

19. The operation method of claim 16 , wherein the plurality of weights are written to a plurality of memory cells in response to the second control signals in a test mode.

Assignees

• Sk Hynix Inc

Inventors

• Shin Jung Soon
• Park Seong Hee
• Kim Ki Young
• Kim Jong Eun

Classifications

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/779

  Circuitry for scanning or addressing the pixel array · CPC title

• H04N25/79

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• H10F39/809

  of hybrid image sensors · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title