Stable scalable digital frequency reference

Patent metadata

Field	Value
Publication number	US-12451893-B2
Application number	US-202418431019-A
Country	US
Kind code	B2
Filing date	Feb 2, 2024
Priority date	Nov 13, 2019
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A method for timing aperture synthesis arrays comprising the steps of: (a) coupling a plurality of independent crystal oscillators, each of the plurality of independent crystal oscillators having a unique output frequency; (b) digitally synchronizing the plurality of independent crystal oscillators in phase; (c) combining the unique output frequencies; and (d) obtaining a stable digital reference signal for timing at least one remote radio device of the aperture synthesis array.

First claim

The invention claimed is:

1. A system for implementing a scalable stable digital frequency reference, the system comprising:
a plurality of independent crystal oscillator circuitry coupled to each other, each of the plurality of independent crystal oscillator circuitry comprising:
(a) an independent crystal oscillator;
(b) a direct digital synthesizer having a first input from the independent crystal oscillator and second input comprising a phase increment clock source cycle to align all direct digital synthesizers in frequency;
(c) a phase sampler for sampling an output phase of each direct digital synthesizer into a common synchronous clock domain;
(d) a sin/cos look-up table stored in a computer-readable medium, wherein the sin/cos look-up table generates a precision digital complex tone based on output of the phase sampler;

a collective coherent vector sum module for combining the precision digital complex tone in-phase to other precision digital complex tone for each of the other direct digital synthesizer to generate a collective coherent vector sum;
a phase management block wherein each of the plurality of independent crystal oscillator circuitry compares its own sin/cos vector with the collective coherent vector sum to determine requisite phase and frequency corrections of its own direct digital synthesizer; and
a conditioner for conditioning the collective coherent vector sum and outputting the scalable stable digital frequency reference.

2. The system of claim 1 , wherein the stable digital frequency reference signal is stable relative to a common and unstable frequency reference signal.

3. The system of claim 1 , wherein the stable digital frequency reference signal is employed in timing at least one remote device.

4. The system of claim 3 , wherein the at least one remote device is a radio telescope.

5. The system of claim 1 , wherein the scalable stable digital frequency reference is used in conjunction with at least one of a packet-switched network communication link and a non-real-time communication link.

6. The system of claim 5 , wherein the conditioner comprises at least one of digital circuitry and analog circuitry.

7. The system of claim 2 , wherein the scalable stable digital frequency reference is used in conjunction with at least one of a packet-switched network communication link and a non-real-time communication link.

8. The system of claim 3 , wherein the scalable stable digital frequency reference is used in conjunction with at least one of a packet-switched network communication link and a non-real-time communication link.

9. The system of claim 4 , wherein the scalable stable digital frequency reference is used in conjunction with at least one of a packet-switched network communication link and a non-real-time communication link.

10. The system of claim 7 , wherein the conditioner comprises at least one of digital circuitry and analog circuitry.

11. The system of claim 8 , wherein the conditioner comprises at least one of digital circuitry and analog circuitry.

Assignees

• Nat Res Council Canada

Inventors

• Carlson Brent

Classifications

• H03L7/24

  using a reference signal directly applied to the generator · CPC title

• H03L7/141

  the phase-locked loop controlling several oscillators in turn · CPC title

• H03B21/04

  using several similar stages · CPC title

• H03B21/02

  by plural beating, i.e. for frequency synthesis {; Beating in combination with multiplication or division of frequency (digital frequency synthesis using a ROM G06F1/02; digital frequency synthesis in general H03K; indirect frequency synthesis using a PLL H03L7/16)} · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title