System and method for predication handling

Patent metadata

Field	Value
Publication number	US-12450009-B2
Application number	US-202217867134-A
Country	US
Kind code	B2
Filing date	Jul 18, 2022
Priority date	May 24, 2019
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

First claim

What is claimed is:

1. A method for writing data to a memory, the method comprising:
for a first iteration of a first loop in a first dimension, receiving a first block of data comprising a plurality of elements;
receiving a total byte count for the first loop;
receiving a width value associated with the first loop;
determining that the total byte count for the first loop exceeds the width value;
disabling a first portion of the first block of data in response to determining that the total byte count exceeds the width value;
enabling a second portion of the first block of data in response to determining that the total byte count exceeds the width value; and
writing only the second portion of the first block of data to the memory.

2. The method of claim 1 , further comprising advancing the total byte count for the first loop until the width value has been met.

3. The method of claim 2 , wherein advancing the total byte count comprises incrementing the total byte count.

4. The method of claim 1 , wherein receiving the total byte count comprises multiplying an iteration count by a width of an iteration of the first loop.

5. The method of claim 4 , wherein determining that the total byte count exceeds the width value comprises determining that a product of the iteration count and the width of the iteration exceeds the width value.

6. The method of claim 1 , wherein determining that the total byte count exceeds the width value comprises advancing the total byte count for each iteration.

7. The method of claim 6 , wherein advancing the total byte count comprises decrementing, for each iteration of the first loop, the total byte count down from the width value until the total byte count reaches or goes below zero.

8. The method of claim 1 , wherein disabling the first portion of the first block of data comprises disabling all bytes after the total byte count exceeds the width value.

9. The method of claim 1 ,
wherein determining that the total byte count exceeds the width value comprises determining that the total byte count saturates the width value, and
wherein the method further comprises disabling all bytes in response to determining that the total byte count saturates the width value.

10. The method of claim 1 , wherein a size of the second portion of the first block of data corresponds to a difference between the width value and a current value of the total byte count.

11. A digital signal processor comprising:
a CPU configured to, for a first iteration of a first loop in a first dimension, receive a first block of data comprising a plurality of memory elements; and
a streaming address generator configured to:
receive a total byte count for the first loop;
receive a width value associated with the first loop;
determine that the total byte count for the first loop exceeds the width value;
disable a first portion of the first block of data in response to determining that the total byte count exceeds the width value; and
enable a second portion of the first block of data in response to determining that the total byte count exceeds the width value,

wherein the CPU is configured to write only the second portion of the first block of data to memory.

12. The digital signal processor of claim 11 , wherein the streaming address generator is further configured to advance the total byte count for the first loop until the width value has been met.

13. The digital signal processor of claim 12 , wherein to advance the total byte count, the streaming address generator is configured to increment the total byte count.

14. The digital signal processor of claim 11 , wherein the streaming address generator is configured to determine the total byte count by at least multiplying an iteration count by a width of an iteration of the first loop.

15. The digital signal processor of claim 14 , wherein to determine that the total byte count exceeds the width value, the streaming address generator is configured to determine that a product of the iteration count and the width of the iteration exceeds the width value.

16. The digital signal processor of claim 11 , wherein to determine that the total byte count exceeds the width value, the streaming address generator is configured to advance the total byte count for each iteration.

17. A digital signal processor system comprising:
a memory; and
a digital signal processor for reading from and writing to the memory, the digital signal processor comprising:
a CPU configured to, for a first iteration of a first loop in a first dimension, receive a first block of data comprising a plurality of memory elements; and
a streaming address generator configured to:
receive a total byte count for the first loop;
receive a width value associated with the first loop;
determine that the total byte count for the first loop exceeds the width value;
disable a first portion of the first block of data in response to determining that the total byte count exceeds the width value; and
enable a second portion of the first block of data in response to determining that the total byte count exceeds the width value,

wherein the CPU is configured to write only the second portion of the first block of data to the memory.

18. The digital signal processor system of claim 17 ,
wherein the streaming address generator is further configured to advance the total byte count for the first loop until the width value has been met, and
wherein to advance the total byte count, the streaming address generator is configured to increment the total byte count.

19. The digital signal processor system of claim 17 , wherein the streaming address generator is configured to determine the total byte count by at least multiplying an iteration count by a width of an iteration of the first loop.

20. The digital signal processor system of claim 19 , wherein to determine that the total byte count exceeds the width value, wherein the streaming address generator is configured to determine that a product of the iteration count and the width of the iteration exceeds the width value.

Assignees

• Texas Instruments Inc

Inventors

• Anderson Timothy David
• Bui Duc Quang
• Zbiciak Joseph
• Krishna Sahithi
• Narnur Soujanya
• Davis Alan

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title