Highly integrated scalable, flexible DSP megamodule architecture

Patent metadata

Field	Value
Publication number	US-9606803-B2
Application number	US-201414331986-A
Country	US
Kind code	B2
Filing date	Jul 15, 2014
Priority date	Jul 15, 2013
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.

First claim

What is claimed is:

1. A digital signal processor comprising:
a data register file including a plurality of data registers designed by register number storing data;
an instruction memory storing instructions each specifying a data processing operation and at least one data operand by register number;
an instruction decoder connected to said instruction memory for sequentially recalling instructions from said instruction memory and determining said specified data processing operation and said specified at least one operand, said instructions including a stream start instruction and a stream operand instruction;
at least one operational unit connected to said data register file and said instruction decoder for performing data processing operations upon at least one operand corresponding to an instruction decoded by said instruction decoder and storing results in an instruction specified data register;
a stream engine connected to said instruction decoder operable in response to a stream start instruction to recall from an external memory a stream of an instruction specified plurality of data elements;
a stream head register distinct from said plurality of data registers of said data register file, connected to said stream engine and readable by said at least one operational unit as an operand, said stream head register sequentially storing a next recalled data element of said stream of the instruction specified plurality of data elements for use as an operand; and
wherein said at least one operational unit is responsive to a stream operand instruction to perform a specified data processing operation determined by the instruction decoder and to receive at least one operand from said stream head register.

2. The digital signal processor of claim 1 , wherein:
said stream operand instruction includes a stream operand read only instruction and a stream operand read and increment instruction;
said at least one operational unit receiving as an operand data stored in said stream head register in response to a stream operand read only instruction and a stream operand read and increment instruction; and
said stream engine storing a next fetched data element in said stream head register in response to a stream operand read and increment instruction.

3. The digital signal processor of claim 1 , wherein:
said stream of the instruction specified plurality of data elements are specified by a start address and an element size.

4. The digital signal processor of claim 3 , wherein:
said specified data size includes 8 bits of data.

5. The digital signal processor of claim 3 , wherein:
said specified data size includes 16 bits of data.

6. The digital signal processor of claim 3 , wherein:
said specified data size includes 32 bits of data.

7. The digital signal processor of claim 3 , wherein:
said specified data size includes 64 bits of data.

8. The digital signal processor of claim 3 , wherein:
said stream head register is divided into plural lanes of said element data size; and
said stream engine stores one data element of said stream in each lane of said stream head register.

9. The digital signal processor of claim 8 , wherein:
if there are fewer remaining data elements than lanes, said stream engine stores all 0's in excess lanes.

10. The digital signal processor of claim 8 , wherein:
said stream engine includes
an address generator generating a memory address of a next data element in said stream of the instruction specified plurality of data elements for fetching said next element from the external memory,
a data first-in-first-out buffer temporarily storing data elements fetched from the external memory, and
a formatter connected to said data first-in-first-out buffer and to said stream head register for recalling data elements from said data first-in-first-out buffer, performing instruction specified formatting upon each data element and storing formatted data elements in said stream head register.

11. The digital signal processor of claim 10 , wherein:
said data first-in-first-out buffer discards stored data elements following supply to said at least one operational unit.

12. The digital signal processor of claim 1 , wherein:
said stream head register is divided into lanes;
said stream specifies promotion or no promotion;
said stream engine
upon specification of no promotion, stores one data element of said stream of the instruction specified plurality of data elements in each lane of said stream head register of said element size, and
upon specification of promotion, promotes the data size of each data element and stores one data element of said stream of the instruction specified plurality of data elements in each lane of said stream head register of twice an original element size.

13. The digital signal processor of claim 12 , wherein:
said stream of the instruction specified plurality of data elements specifies a data type including an unsigned integer data type; and
said stream engine upon specification of promotion, promotes the data size of each unsigned integer data type data element by zero extension.

14. The digital signal processor of claim 12 , wherein:
said stream of the instruction specified plurality of data elements specifies a data type including a signed integer data type; and
said stream engine upon specification of promotion, promotes the data size of each signed integer data type data element by sign extension.

15. The digital signal processor of claim 12 , wherein:
said stream of the instruction specified plurality of data elements specifies a data type including a floating point number data type; and
said stream engine upon specification of promotion, promotes a floating point number having a data size of 16 bits from a short (16-bit) floating point number to a single precision (32-bit) floating point number.

16. The digital signal processor of claim 12 , wherein:
said stream of the instruction specified plurality of data elements specifies a data type including a floating point number data type; and
said stream engine upon specification of promotion, promotes a floating point number having a data size of 32 bits from a single precision (32-bit) floating point number to a double precision (64-bit) floating point number.

17. The digital signal processor of claim 1 , wherein:
said stream of the instruction specified plurality of data elements specifies a data type including a complex number data type; and
said specified data size includes two equal sized sub-elements of data for said complex number data type.

18. The digital signal processor of claim 17 , wherein:
each of said two equal sized sub-elements of data includes 8 bits.

19. The digital signal processor of claim 17 , wherein:
each of said two equal sized sub-elements of data includes 16 bits.

20. The digital signal processor of claim 17 , wherein:
each of said two equal sized sub-elements of data includes 32 bits.

21. The digital signal processor of claim 17 , wherein:
each of said two equal sized sub-elements of data includes 64 bits.

22. The digital signal processor of claim 17 , wherein:
said stream head register is divided into lanes;
said stream of the instruction specified plurality of data elements specifies no swap or swap for said complex number data type;
said stream engine
upon specification of no swap for a complex number data type, storing said two sub-elements of a complex number fetched data element in a lane

Assignees

• Texas Instruments Inc

Inventors

• Anderson Timothy D
• Zbiciak Joseph
• Bui Duc Quang
• Chachad Abhijeet A
• Chirca Kai
• Bhoria Naveen
• Pierson Matthew D
• Wu Daniel
• Venkatasubramanian Ramakrishnan

Classifications

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/345 Primary

  of multiple operands or results {(addressing multiple banks G06F12/06)} · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title

• G06F9/3822

  Parallel decoding, e.g. parallel decode units · CPC title