Regulator providing shared current from multiple input supplies

Patent metadata

Field	Value
Publication number	US-12449833-B2
Application number	US-202217876323-A
Country	US
Kind code	B2
Filing date	Jul 28, 2022
Priority date	Mar 11, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

Various embodiments of the present disclosure relate to apparatuses and methods for regulators providing shared current from multiple input supplies. A regulator can include a first portion configured to receive a first supply voltage and to output a first current drawn from the first supply voltage by a load, and a second portion configured to receive a second supply voltage. The regulator can include a current control circuit configured to, responsive to a load current corresponding the load meeting a particular criteria, initiate current sharing such that the load current is subsequently shared between the first supply voltage and the second supply voltage.

First claim

What is claimed is:

1. A voltage regulator, comprising:
a first portion configured to receive a first supply voltage and to output a first current drawn from the first supply voltage by a load;
a second portion configured to receive a second supply voltage, the second supply voltage being received from a different input supply than the first supply voltage; and
a current control circuit configured to, responsive to a load current corresponding to the load meeting a current sharing point, initiate current sharing of the load current between the first supply voltage and the second supply voltage; and
wherein the first portion includes an error amplifier having an output coupled to a gate of a pass transistor and directly connected to the current control circuit.

2. The voltage regulator of claim 1 , wherein second portion includes a transistor having a first source/drain configured to receive the second supply voltage and a second source/drain configured to provide a portion of the load current subsequent to the load current meeting the current sharing point.

3. The voltage regulator of claim 1 , wherein the current control circuit comprises one or more current mirrors.

4. The voltage regulator of claim 3 , wherein a first current mirror of the one or more of current mirrors comprises the pass transistor of the first portion.

5. The voltage regulator of claim 3 , wherein the load current shared by the first supply voltage and the second supply voltage includes a first load current portion provided by the first supply voltage and a second load current portion that is provided by the second supply voltage, and wherein the second load current portion is generated by a replica current from the first load current portion.

6. The voltage regulator of claim 1 , wherein the current control circuit comprises at least two current mirrors, wherein at least two of the current mirrors have different mirror ratios.

7. The voltage regulator of claim 1 , wherein the current sharing point is the load current reaching a threshold current value, and wherein the current control circuit comprises a programmable current source used to set the threshold current value.

8. The voltage regulator of claim 1 , wherein the voltage regulator is a low dropout (LDO) regulator.

9. A method, comprising:
receiving a first supply voltage at a first portion of a voltage regulator, the voltage regulator configured to provide an output current drawn by a load;
receiving a second supply voltage at a second portion of the voltage regulator, the second supply voltage being received from a different input supply than the first supply voltage;
prior to the output current drawn by the load meeting a current sharing point, providing the output current from only the first supply voltage; and
responsive to the output current drawn by the load meeting the current sharing point, initiating, via a current control circuit of the voltage regulator, current sharing between the first supply voltage and the second supply voltage of the voltage regulator, wherein the output current is provided by both the first supply voltage and the second supply voltage; and
wherein the first portion includes an error amplifier having an output coupled to a gate of a pass transistor and directly connected to the current control circuit.

10. The method of claim 9 , wherein the current sharing point corresponds to the output current drawn by the load reaching a threshold current value, and wherein the method includes sharing the output current provided by the first supply voltage and the second supply voltage in accordance with a particular current sharing ratio.

11. The method of claim 10 , wherein the method includes adjusting the threshold current value via a programmable current source of the current control circuit.

12. The method of claim 10 , wherein the voltage regulator is part of a memory system, wherein the first supply voltage is provided from a host to which the memory system is coupled, and wherein the method includes initiating the current sharing to avoid current drawn from the first supply voltage from reaching or exceeding a peak current draw allowed by the host.

13. The method of claim 9 , wherein the method includes:
receiving a third supply voltage at a third portion of the voltage regulator, the third supply voltage being received from a different input than both the first supply voltage and the second supply voltage; and
responsive to the output current drawn by the load meeting another current sharing point, initiating, via the current control circuit of the voltage regulator, current sharing between the first supply voltage, the second supply voltage, and the third supply voltage of the voltage regulator such that the output current is provided by the first, the second, and the third supply voltages.

14. An apparatus, comprising:
one or more memory components of a memory system; and
a controller of the memory system coupled to the one or more memory components and comprising regulator circuitry configured to provide power to various portions of the memory system;
wherein the regulator circuitry comprises a regulator having a first input power supply and a second input power supply, the second input power supply being a different input supply than the first input power supply; and
wherein the regulator is configured to:
provide load current from the first input power supply until the load current meets a current sharing point; and
responsive to the load current meeting the current sharing point, split the load current between the first input power supply and the second input power supply; and

wherein the regulator includes an error amplifier having an output coupled to a gate of a first pass transistor coupled to the first input power supply, and wherein the second input power supply is coupled to a second pass transistor whose gate is coupled to a current control circuit configured to activate current sharing between the first input power supply and the second input power supply when the load current reaches the current sharing point.

15. The apparatus of claim 14 , wherein the regulator is a low dropout (LDO) voltage regulator.

16. The apparatus of claim 15 , wherein the current control circuit comprises one or more current mirrors configured to provide a particular current sharing ratio of a portion of the load current provided by the first input power supply to a portion of the load current provided by the second input power supply.

17. The apparatus of claim 14 , wherein:
the current sharing point corresponds to the load current reaching a threshold current value; and
the regulator is configured to receive the first input power supply from a host, wherein the host is prevented from allowing a provision of more than a particular amount of current from being drawn from the first input power supply.

18. The apparatus of claim 14 , wherein the memory components comprise NOT AND (NAND) memory components, wherein the first input power supply is an input/output (I/O) supply, and wherein the second input power supply is a different supply having a higher voltage than the I/O supply.

19. The apparatus of claim 14 , wherein the memory system is one of a solid-state drive (SSD), a Universal Flash Storage (UFS) device, and an embedded Multiple Media Card (eMMC).

Assignees

• Micron Technology Inc

Inventors

• Bhuiyan Ekram H
• Naradasi Jayaprakash
• Sabbineni Srinivasa Rao
• Mostovoy Michael

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G05F1/56

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G05F1/59 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title