Regulation/bypass automation for LDO with multiple supply voltages

Patent metadata

Field	Value
Publication number	US-10444780-B1
Application number	US-201816136305-A
Country	US
Kind code	B1
Filing date	Sep 20, 2018
Priority date	Sep 20, 2018
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

Regulation/Bypass automation for a low drop-out regulator (LDO) with multiple supply voltages is disclosed. In some implementations, a LDO includes a resistor, a pass transistor having a source, a gate, and a drain to output a voltage Vout, the source coupled to a supply voltage, the gate coupled to an output of an operational transconductance amplifier (OTA), and the drain coupled to a first terminal of the resistor; a feedback switch having a drain, a gate, and a source, the drain coupled to a second terminal of the resistor, the source coupled to a negative input of the OTA; and an pull-down transistor having a drain, a gate, and a source, the source coupled to ground, and the drain coupled to the negative input of the OTA, wherein the gate of the pull-down transistor and the gate of the feedback switch are configured to receive a bypass signal.

First claim

What is claimed is:

1. A low drop-out regulator (LDO), comprising:
a first resistor having a first terminal and a second terminal;
a pass transistor having a source, a gate, and a drain to output a voltage Vout, the source coupled to a supply voltage, the gate coupled to an output of an operational transconductance amplifier (OTA), and the drain coupled to the first terminal of the first resistor;
a feedback switch having a drain, a gate, and a source, the drain coupled to the second terminal of the first resistor, the source coupled to a negative input of the OTA; and
an pull-down transistor having a drain, a gate, and a source, the source coupled to ground, the gate coupled to the gate of the feedback switch, and the drain coupled to the negative input of the OTA, wherein the gate of the pull-down transistor and the gate of the feedback switch are configured to receive a bypass signal.

2. The LDO of claim 1 , further comprising:
a second resistor having a first terminal and a second terminal, the second terminal coupled to ground and the first terminal coupled to the second terminal of the first resistor.

3. The LDO of claim 1 , wherein the bypass signal is asserted when the supply voltage is at approximately 1.8V.

4. The LDO of claim 3 , wherein the LDO enters a bypass mode when the bypass signal is asserted.

5. The LDO of claim 4 , wherein, in response to the bypass signal being asserted, the pull-down transistor pulls the negative input of the OTA to ground.

6. The LDO of claim 1 , wherein the bypass signal is de-asserted when the supply voltage is at approximately 3.3V or 5.0V.

7. The LDO of claim 6 , wherein the LDO enters a regulation mode when the bypass signal is de-asserted.

8. The LDO of claim 7 , wherein, in response to the bypass signal being de-asserted, the feedback switch is closed to cause the pass transistor to output a regulated voltage at approximately 1.8V.

9. The LDO of claim 1 , wherein the supply voltage is within a range of approximately 5V to 1.8V.

10. The LDO of claim 1 , wherein the feedback switch comprises a first p-type transistor, the pull-down transistor is an n-type transistor, and the pass transistor is a second p-type transistor.

Assignees

• Qualcomm Inc

Inventors

• Cheng Yueh Chun
• Cheng Hung-Min
• Lin Chien-Chih

Classifications

• H03F2203/45674

  the LC comprising one current mirror · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title