Memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12446226-B2
Application number	US-202217697221-A
Country	US
Kind code	B2
Filing date	Mar 17, 2022
Priority date	Sep 24, 2021
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A memory device, and a method of manufacturing the same, includes a source layer over which a cell region and a peripheral circuit region are defined, memory blocks formed on the source layer in the cell region, and a slit formed between the memory blocks. The memory device also includes a resistor formed in the source layer in the peripheral circuit region, contacts formed on the resistor, and metal lines formed on the contacts and connected to a peripheral circuit.

First claim

What is claimed is:

1. A memory device comprising:
a source layer over which a cell region and a peripheral circuit region are defined;
memory blocks formed on the source layer in the cell region;
a slit formed between the memory blocks;
a resistor formed in the source layer in the peripheral circuit region;
contacts formed on the resistor; and
metal lines formed on the contacts and connected to a peripheral circuit.

2. The memory device of claim 1 , further comprising:
a first insulating layer extending between the cell region and the peripheral circuit region.

3. The memory device of claim 1 , further comprising a resistor unit, wherein the resistor unit comprises the resistor, the contacts, and the metal lines.

4. The memory device of claim 3 , wherein a resistance value of the resistor unit is based on a distance between the contacts and a material of the resistor.

5. The memory device of claim 1 , wherein the resistor comprises at least one of tungsten (W), titanium (Ti), and titanium nitride (TiN).

6. The memory device of claim 1 , wherein the resistor is formed in a slit region in which the slit is formed.

7. The memory device of claim 1 , further comprising:
a second insulating layer formed around and under the resistor to electrically isolate the resistor from the source layer in the peripheral circuit region.

8. The memory device of claim 1 , further comprising:
a dummy structure formed on the source layer in the peripheral circuit region.

9. The memory device of claim 8 , wherein the dummy structure includes first material layers and second material layers alternately stacked on the source layer.

10. The memory device of claim 9 , wherein:
the first material layers comprise oxide layers, and
the second material layers comprise nitride layers.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Taek
• Jung Hye Yeong

Classifications

• H10B41/41

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title

• H10D84/209

  of only resistors · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10B43/40 Primary

  characterised by the peripheral circuit region · CPC title

• H10D1/47

  Resistors having no potential barriers · CPC title