Offset compensated analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-12445146-B2
Application number	US-202318517124-A
Country	US
Kind code	B2
Filing date	Nov 22, 2023
Priority date	Nov 22, 2023
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

An oversampling analog-to-digital converter (ADC) may include a quantizer that adds an offset error to each oversampling sample. If not reduced, the offset error may limit the performance of the ADC. The existing methods to eliminate the offset may increase a circuit size and slow the operation of the ADC. An oversampling ADC that can reduce, or remove, the offset error is disclosed. The disclosed ADC can be small and fast and still remove the offset. Accordingly, the disclosed ADC may be used in high performance applications, such as a high-speed image sensor.

First claim

The invention claimed is:

1. A method for compensating for an offset voltage in a sigma-delta ADC, the method comprising:
replacing an input voltage for a first conversion of a set of conversions, at an input of the sigma-delta ADC, with a reference voltage;
quantizing the reference voltage, at a quantizer of the sigma-delta ADC, to obtain a dummy sample, the dummy sample including the offset voltage added by the quantizer of the sigma-delta ADC;
decoupling a decimation filter of the sigma-delta ADC;
generating a feedback voltage, corresponding to the dummy sample, the feedback voltage including the offset voltage;
inverting the feedback voltage to generate an inverted feedback voltage;
applying the inverted feedback voltage to an integrator of the sigma-delta ADC, the inverted feedback voltage including an inverted offset voltage; and
storing the inverted offset voltage in the integrator to generate an offset-charged integrator.

2. The method according to claim 1 , wherein:
the set of conversions are performed to generate an output sample; and
for conversions other than the first conversion of the set of conversions, the inverted offset voltage added by the offset-charged integrator cancels the offset voltage added by the quantizer while generating the output sample.

3. The method according to claim 2 , wherein the set of conversions is a first set of conversions and the output sample is a first output sample, and wherein after performing the first set of conversions to generate the first output sample, the method further comprises:
resetting the offset-charged integrator by clearing the inverted offset voltage before starting a second set of conversions to generate a second output sample; and
generating a second offset-charged integrator for the second set of conversions.

4. The method according to claim 3 , wherein performing the set of conversions to generate the output sample further includes:
receiving the input voltage at the input of the sigma-delta ADC;
applying the input voltage to the offset-charged integrator;
applying an integrator output of the offset-charged integrator to the quantizer, the integrator output including the inverted offset voltage to cancel the offset voltage added by the quantizer;
generating an oversampling sample, the oversampling sample having no offset error; and
applying the oversampling sample to the decimation filter.

5. The method according to claim 2 , wherein:
the first conversion of the set of conversions is the dummy sample, which is not accumulated by the decimation filter; and
the conversions other than the first conversion of the set of conversions are oversampling samples that are accumulated by the decimation filter.

6. The method according to claim 5 , wherein:
storing the inverted offset voltage stored in the integrator is based on the dummy sample and not the oversampling samples.

7. The method according to claim 5 , further comprising:
outputting the output sample corresponding to the input voltage at an output of the decimation filter is based on the oversampling samples and not the dummy sample.

8. The method according to claim 1 , wherein for the first conversion of the set of conversions, the method further includes:
adding a pedestal voltage to the reference voltage; and
storing the pedestal voltage in the integrator with the inverted offset voltage.

9. The method according to claim 8 , further comprising:
not adding the pedestal voltage to conversions other than the first conversion of the set of conversions.

10. The method according to claim 1 , wherein the reference voltage is zero volts.

11. A method for compensating for an offset error in a sigma-delta ADC:
performing a set of conversions to generate an output sample, wherein for a first conversion of the set of conversions, the method includes:
replacing an input voltage at an input of the sigma-delta ADC with a reference voltage;
bypassing an integrator of the sigma-delta ADC;
quantizing the reference voltage, at a quantizer of the sigma-delta ADC, to obtain a dummy sample, the dummy sample including the offset error added by the quantizer of the sigma-delta ADC; and
applying the dummy sample to a decimation filter configured to store the offset error to generate an offset-compensated decimation filter, the offset-compensated decimation filter configured to subtract the offset error added by the quantizer of the sigma-delta ADC for conversions other than the first conversion of the set of conversions.

12. The method according to claim 11 , wherein the set of conversions is a first set of conversions an the output sample is a first output sample, and wherein after performing the first set of conversions to generate the first output sample, the method further comprises:
resetting the offset-compensated decimation filter by clearing the offset error before starting a second set of conversions to generate a second output sample; and
generating a second offset-compensated decimation filter configured for the second set of conversions.

13. The method according to claim 11 , wherein performing the set of conversions to generate the output sample further includes:
receiving the input voltage and a feedback voltage at the integrator;
applying an integrator output to the quantizer to generate an oversampling sample, the oversampling sample including the offset error added by the quantizer;
applying the oversampling sample to the offset-compensated decimation filter, the offset-compensated decimation filter subtracting the offset error added by the quantizer from the oversampling sample; and
accumulating the oversampling sample in the decimation filter, which is configured to accumulate oversampling samples generated by the conversions other than the first conversion.

14. The method according to claim 13 , wherein:
the first conversion of the set of conversions does not include the integrator to generate the dummy sample; and
the conversions other than the first conversion of the set of conversions includes the integrator to generate the oversampling samples.

15. The method according to claim 14 , further comprising:
the output sample is based on the oversampling samples and is not based on the dummy sample.

16. The method according to claim 11 , wherein the method further includes:
adding a pedestal voltage as negative feedback to the input of the sigma-delta ADC at a start of each conversion of the set of conversions.

17. A sigma-delta ADC comprising:
a sigma-delta modulator including:
an integrator configured to store a difference between an input voltage and a feedback voltage; and
a quantizer configured to generate an oversampling sample based on an integrator-output voltage of the integrator, the oversampling sample including an offset error;

a decimation filter coupled to an output of the sigma-delta modulator and configured to receive the oversampling sample from the quantizer; and
control logic configured by instructions and/or logic circuitry to:
configure the sigma-delta modulator to perform a set of conversions to generate an output sample;
replace, for a first conversion of the set of conversions, the input voltage with a zero voltage; and
decouple, for the first conversion of the set of conversions, the decimation filter from the quantizer so that the feedback voltage from the output of the quantizer is an offset voltage corresponding to the offset error, the offset voltage being stored in the integrator.

18. The sigma-delta ADC according to claim 17 , wherein t

Assignees

• Semiconductor Components Ind Llc

Inventors

• Gurindagunta Sundaraiah
• Sampath Parthasarathy V

Classifications

• H03M3/428 Primary

  with lower resolution, e.g. single bit, feedback · CPC title

• H03M3/456

  the modulator having a first order loop filter in the feedforward path · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/384

  Offset correction (removal of offset already present on the analogue input signal H03M3/494) · CPC title