Memory device and operating method thereof, memory system and operating method thereof

Patent metadata

Field	Value
Publication number	US-12443522-B2
Application number	US-202418595864-A
Country	US
Kind code	B2
Filing date	Mar 5, 2024
Priority date	Nov 6, 2023
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

Examples of the present application disclose a memory device and operating method thereof, a memory system and operating method thereof, wherein the memory device includes: an array of memory cells; peripheral circuit coupled to the array of memory cells and configured to: obtain the first state corresponding to at least one code word formed by a preset number of memory cells at the target read voltage; perform multiple adjustments to the target read voltage, and obtain a first state corresponding to the at least one of the code words at the read voltage after each of the adjustments respectively; determine a valley voltage in accordance with a variation trend of the relationship of size between the number of flipped bits and the first preset value indicated by a plurality of the obtained first states.

First claim

What is claimed is:

1. A memory device, comprising:
an array of memory cells, including a plurality of memory cells; wherein a preset number of the memory cells forms a code word; and
a peripheral circuit coupled to the array of memory cells and configured to:
obtain a first state corresponding to at least one of the code words at a target read voltage; wherein the first state includes a state that represents a relationship of size between a number of bits in the at least one of the code words which are flipped in two results of reading at a first read voltage and a second read voltage and a first preset value; and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage;

read data stored in at least one of the code words at the target read voltage to obtain a first result;
perform a first adjustment to the target read voltage and read data stored in at least one of the code words at an adjusted target read voltage to obtain a second result;
perform a logical operation on the first result and the second result to obtain a third result;
compare the number of bits in the third result that represent flip of bits in the second result relative to the first result and the first preset value to obtain a first state; and
determine a valley voltage in accordance with a variation trend of the relationship of size between the number of flipped bits and the first preset value indicated by the first state; wherein the valley voltage is a read voltage for performing a read operation on the at least one of the code words.

2. The memory device of claim 1 , wherein the peripheral circuit includes:
a first latch configured to store the first result;
a second latch configured to store the second result; and
a third latch configured to store the third result.

3. The memory device of claim 1 , wherein:
when the number of bits in the third result that represent flip of bits in the second result relative to the first result is greater than the first preset value, the first state is a failed state; and
when the number of bits in the third result that represent flip of bits in the second result relative to the first result is less than or equal to the first preset value, the first state is a pass state.

4. The memory device of claim 3 , wherein the peripheral circuit is configured to:
when multiple adjustments are performed to the target read voltage, perform a second adjustment to the read voltage after a previous adjustment for each of the multiple adjustments; wherein a step size of the second adjustment is greater than that of the first adjustment; and wherein the step size of the second adjustment is a fixed value; and
when multiple adjustments are performed to the target read voltage, if a change from a failed state to at least one pass state and then to a failed state again is indicated by a plurality of the first states corresponding to the read voltages after multiple adjustments, stop adjusting the read voltage.

5. The memory device of claim 4 , wherein:
when a number of pass states between the failed states at two ends indicated by a plurality of first states corresponding to adjusted read voltages include one, an adjusted read voltage corresponding to the one pass state is the valley voltage;
when the number of pass states between the failed states at two ends indicated by the plurality of first states corresponding to the adjusted read voltages include more than one, the adjusted read voltage corresponding to one pass state at a middle position among the more than one pass states is the valley voltage; and
when the number of pass states between the failed states at two ends indicated by the plurality of first states corresponding to the adjusted read voltages includes an even number, an average of the adjusted read voltages corresponding to two pass states at a middle position among the plurality of the pass states is the valley voltage.

6. The memory device of claim 4 , wherein the peripheral circuit is configured to:
after a first pass state after failed states occurs among a plurality of first states corresponding to the read voltages after multiple adjustments, perform a third adjustment to the read voltage after a previous adjustment; wherein the step size of the third adjustment is less than that of the second adjustment.

7. The memory device of claim 6 , wherein the peripheral circuit is configured to:
maintain the third adjustment until a first failed state after pass states occurs among the plurality of first states; and
after the first failed state after pass states occurs among the plurality of first states, perform the second adjustment to the read voltage after a previous adjustment.

8. The memory device of claim 4 , wherein the peripheral circuit is configured to:
after a first pass state after failed states occurs among a plurality of first states corresponding to the read voltages after multiple adjustments, perform a fourth adjustment to the read voltage after a previous adjustment in accordance with the third result corresponding to the first pass state.

9. The memory device of claim 4 , wherein the peripheral circuit is configured to:
when a plurality of first states corresponding to the read voltages after multiple adjustments are all failed states, increase the step size corresponding to the second adjustment; and
when an increased step size of the second adjustment exceeds a second preset value, adjust a number of memory cells corresponding to at least one of the code words; wherein the number of memory cells corresponding to the code word after adjustment is less than the number of memory cells corresponding to the code word before adjustment.

10. The memory device of claim 1 , wherein the peripheral circuit is configured to:
obtain the first preset value; wherein the first preset value is obtained in accordance with historical data and less than an upper limit of a fail bit count supported by the memory device.

11. The memory device of claim 1 , wherein the peripheral circuit is configured to:
before obtaining the first state corresponding to at least one of the code words at the target read voltage, set a read mode of the memory device to a single level read mode; wherein the single level read mode includes reading at least one bit of storage data stored in the memory cell with read voltages at one level.

12. The memory device of claim 11 , wherein:
the memory cell includes M bits, the memory device includes M-type pages, and the memory cell with M bits reads its M bits of storage data with read voltages at N levels;
the M and N are both integers greater than 1, and N=2 M −1; and
the peripheral circuit is configured to:
for read voltages at each level of the read voltages at multiple levels corresponding to each type of page, determine the valley voltage at each level in accordance with a plurality of first states corresponding to multiple read voltages at each level.

13. The memory device of claim 1 , wherein the first state is a pass state or a failed state.

14. A memory system, comprising:
one or more memory devices, comprising:
an array of memory cells; wherein the array of memory cells includes a plurality of memory cells; and wherein a preset number of the memory cells forms a code word;
a peripheral circuit coupled to the array of memory cells and configured to:
obtain a first state corresponding to at least one of the code words at a target read voltage; wherein the first state includes a state that represents a relationship of size between a number of bits in the at least one of the code words which are flipped in

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Tang Xingwei
• Ye Guangchang
• Guo Lu

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/021 Primary

  in voltage or current generators · CPC title

• G11C29/028 Primary

  with adaption or trimming of parameters · CPC title