Single page read level tracking by bit error rate analysis

Patent metadata

Field	Value
Publication number	US-11244732-B2
Application number	US-201916364347-A
Country	US
Kind code	B2
Filing date	Mar 26, 2019
Priority date	Sep 28, 2018
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A method for calibrating read threshold voltages includes receiving, from at least one memory die, a number of page bits corresponding to a number of read operations performed on a page associated with the at least one memory die. The method further includes determining voltage bins for each bit of the number of page bits. The method further includes determining, for each voltage bin, a bit error rate. The method further includes adjusting read threshold voltages associated with the at least one memory die using the bite error rate for each voltage bin.

First claim

What is claimed is:

1. A method for calibrating read threshold voltages, the method comprising:
performing a plurality of read operations on at least one memory die;
for each memory state resultant from the plurality of read operations, determining a corresponding voltage bin of a plurality of voltage bins;
determining, for each of the plurality of voltage bins, a bit error rate;
calculating a Gaussian tail distribution function for each respective voltage bin using the bit error rate corresponding to the respective voltage bin;
determining a distance of a read threshold associated with the at least one memory die from an optimal read threshold for each respective voltage bin using the Gaussian tail distribution function corresponding to the respective voltage bin; and
adjusting the read threshold voltages using the distance of the read threshold from the optimal read threshold voltage for each of the plurality of voltage bins.

2. The method of claim 1 , further comprising flipping logical values of erroneous bits associated with each of the plurality of voltage bins.

3. The method of claim 2 , wherein the determining, for each of the plurality of voltage bins, the bit error rate, comprises, for each of the plurality of voltage bins, determining a first number of bits flipped from a first value to a second value and determining a second number of bits flipped from the second value to the first value.

4. The method of claim 3 , wherein the adjusting the read threshold voltages comprises adjusting the read threshold voltages based on whether the first number is greater than the second number.

5. The method of claim 1 , wherein the determining, for each of the plurality of voltage bins, the bit error rate, comprises, for each of the plurality of voltage bins, estimating the bit error rate using a corresponding syndrome weight.

6. The method of claim 1 , wherein the performing the plurality of read operations comprises performing a plurality of host read operations.

7. The method of claim 1 , wherein the adjusting the read threshold voltages comprises determining a voltage shift value for each respective read threshold voltage.

8. The method of claim 7 , wherein the voltage shift value for each respective read threshold voltage is determined using the Gaussian tail distribution function for the respective voltage bin corresponding to the respective read threshold voltage.

9. The method of claim 7 , wherein the adjusting the read threshold voltages further comprises shifting each respective read threshold voltage by the determined voltage shift value.

10. A controller comprising:
a bus interface configured to receive, from at least one memory die, a result of a plurality of read operations performed on the at least one memory die; and
a processor configured to:
for each memory state resultant from the plurality of read operations, determine a corresponding voltage bin of a plurality of voltage bins;
determine, for each of the plurality of voltage bins, a bit error rate;
calculate a Gaussian tail distribution function for each respective voltage bin using the bit error rate corresponding to the respective voltage bin;
determine a distance of a read threshold associated with the at least one memory die from an optimal read threshold for each respective voltage bin using the Gaussian tail distribution function corresponding to the respective voltage bin; and
adjust the read threshold voltages using the distance of the read threshold from the optimal read threshold voltage for each of the plurality of voltage bins.

11. The controller of claim 10 , wherein the processor is further configured to flip logical values of erroneous bits associated with each of the plurality of voltage bins.

12. The controller of claim 11 , wherein the processor is further configured to determine, for each of the plurality of voltage bins, the bit error rate by determining a first number of bits flipped from a first value to a second value and determining a second number of bits flipped from the second value to the first value.

13. The controller of claim 12 , wherein the processor is further configured to adjust the read threshold voltages by adjusting the read threshold voltages based on whether the first number is greater than the second number.

14. The controller of claim 10 , wherein the processor is further configured to determine, for each of the plurality of voltage bins, the bit error rate by estimating the bit error rate using a corresponding syndrome weight.

15. The controller of claim 10 , wherein the plurality of read operations comprise host read operations.

16. The controller of claim 10 , wherein the processor is further configured to adjust the read threshold voltages by determining a voltage shift value for each respective read threshold voltage.

17. The controller of claim 16 , wherein the processor is further configured to determine the voltage shift value for each respective read threshold voltage using the Gaussian tail distribution function for the respective voltage bin corresponding to the respective read threshold voltage.

18. The controller of claim 16 , wherein the processor is further configured to adjust the read threshold voltages by shifting each respective read threshold voltage by the determined voltage shift value.

19. A system for calibrating read threshold voltages, the system comprising:
a controller in communication with at least one memory die, the controller configured to:
receive, from the at least one memory die, a result of a plurality of operations performed on the at least one memory die;
for each memory state resultant from the plurality of read operations, determine a voltage bin of a plurality of voltage bins;
determine, for each of the plurality of voltage bins, a bit error rate;
calculate a Gaussian tail distribution function for each respective voltage bin using the bit error rate corresponding to the respective voltage bin;
determine a distance of a read threshold associated with the at least one memory die from an optimal read threshold for each respective voltage bin using the Gaussian tail distribution function corresponding to the respective voltage bin; and
adjust the read threshold voltages using the distance of the read threshold from the optimal read threshold voltage for each of the plurality of voltage bins, wherein each of the plurality of voltage bins corresponds to a respective read threshold voltage.

20. The system of claim 19 , wherein the controller is further configured to determine, for each of the plurality of voltage bins, the bit error rate using a corresponding syndrome weight.

Assignees

• Western Digital Tech Inc

Inventors

• Sharon Eran
• Bazarsky Alex
• Alrod Idan

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title