Systems and methods for coherent power management

Patent metadata

Field	Value
Publication number	US-12443260-B2
Application number	US-202318523819-A
Country	US
Kind code	B2
Filing date	Nov 29, 2023
Priority date	Feb 13, 2017
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g., with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

First claim

What is claimed is:

1. An apparatus comprising:
a processing circuit;
a power management circuit including at least one voltage regulator configured to supply power to the processing circuit;
a plurality of monitoring circuits configured to monitor power conditions of the processing circuit, the power conditions including at least one electrical parameter of the power supplied to the processing circuit, wherein a given one of the plurality of monitor circuits is configured to operate in a different one of a plurality of time domains concurrent with other ones of the plurality of monitoring circuits operating in respective different ones of the plurality of time domains, wherein a time characteristic corresponding to a given one of the plurality of time domains is different in magnitude from a magnitude of a time characteristic corresponding to another one of the plurality of time domains; and
a plurality of compensation circuits, wherein ones of the plurality of compensation circuits are configured to implement one or more corrective actions in response to variations in the power conditions as detected by ones of the plurality of monitoring circuits, wherein a given one of the plurality of compensation circuits is configured to operate in a different one of the plurality of time domains concurrent with other ones of the plurality of compensation circuits operating in respective different ones of the plurality of time domains.

2. The apparatus of claim 1 , further comprising a plurality of transfer circuits, wherein ones of the plurality of transfer circuits are configured to transfer data between ones of the plurality of time domains, and wherein a given one of the plurality of compensation circuits is configured to carry out a corrective action in response to data input from multiple ones of the plurality of time domains.

3. The apparatus of claim 1 , wherein the time characteristic corresponding to the given one of the plurality of time domains is different by one or more orders of magnitude with respect to the time characteristic corresponding to another one of the plurality of time domains.

4. The apparatus of claim 3 , wherein a first time characteristic for a first time domain of the plurality of time domains is different from a second time characteristic for a second time domain of the plurality of time domains by one or more orders of magnitude.

5. The apparatus of claim 1 , wherein the time characteristic of a first one of the plurality of time domains is a first bandwidth and wherein the time characteristic of a second one of the plurality of time domains is a second bandwidth different from the first bandwidth.

6. The apparatus of claim 1 , wherein the time characteristic of a first one of the plurality of time domains is a first latency and wherein the time characteristic of a second one of the plurality of time domains is a second latency different from the first latency.

7. The apparatus of claim 1 , wherein the processing circuit and at least one of the plurality of monitoring circuits are integrated onto a common integrated circuit.

8. The apparatus of claim 7 , wherein the power management circuit is implemented externally with respect to the common integrated circuit.

9. A method comprising:
monitoring, using a plurality of monitoring circuits, one or more parameters of electrical power provided to an integrated circuit, a given one of the plurality of monitoring circuits operating in a different one of a plurality of time domains concurrent with other ones of the plurality of monitoring circuits operating in respective different ones of the plurality of time domains and according to a respective time characteristic that is different with respect to the other ones of the plurality of monitoring circuits, wherein respective time characteristics of the ones of the plurality of monitoring circuits differ in magnitude from respective time characteristics of the other ones of the plurality of monitoring circuits;
compensating, using a plurality of compensation mechanisms implemented by ones of a plurality of compensation circuits, for variations in the electrical power provided to the integrated circuit, wherein a given one of the plurality of compensation circuits is configured to operate in a different one of the plurality of time domains concurrent with other ones of the plurality of compensation circuits operating in respective different ones of the plurality of time domains, and wherein the given one of the plurality of compensation circuits is further configured to operate concurrent with and according to different time characteristics with respect to other ones of the plurality of compensation circuits; and
coordinating operation of the plurality of compensation mechanisms when the plurality of compensation mechanisms are reacting to a same variation in the electrical power to the integrated circuit.

10. The method of claim 9 , wherein the different time characteristics differ from one another by one or more orders of magnitude.

11. The method of claim 9 , further comprising compensating, using the plurality of compensation mechanisms, for variations in power provided to one or more processing circuits implemented on the integrated circuit.

12. A system comprising:
an integrated circuit, wherein the integrated circuit includes at least one processing circuit and a coherent power management circuit; and
a plurality of telemetry circuits external to the integrated circuit, wherein a given one of the plurality of telemetry circuits is configured to operate in a different one of a plurality of time domains concurrent with other ones of the plurality of telemetry circuits operating in respective different ones of the plurality of time domains and in accordance with a respective one of a plurality of time characteristics, wherein ones of the plurality of time characteristics have a magnitude different from other ones of the plurality of time characteristics; and
a plurality of limiting circuits, wherein ones of the plurality of limiting circuits are coupled to respective ones of the plurality of telemetry circuits, wherein ones of the plurality of limiting circuits are configured to limit activity in the at least one processing circuit, wherein ones of the plurality of limiting circuits are configured to communicate with the coherent power management circuit via ones of the plurality of telemetry circuits.

13. The system of claim 12 , wherein at least a first limiting circuit of the plurality of limiting circuits is configured to cause a limitation of issuance of instructions for execution by the at least one processing circuit, and wherein at least a second limiting circuit of the plurality of limiting circuits is configured to cause dithering of a clock signal provided to the at least one processing circuit.

14. The system of claim 12 , wherein at least one of the plurality of limiting circuits is configured to cause a reduction of a frequency of a clock signal provided to the at least one processing circuit.

15. The system of claim 12 , wherein at least one of the plurality of limiting circuits is configured to cause gating of a clock signal provided to the at least one processing circuit.

16. The system of claim 12 , wherein the plurality of time characteristics include first, second and third time characteristics, wherein the second time characteristic is at least one order of magnitude greater than the first time characteristic, and wherein the third time characteristic is at least one order of magnitude greater than the second time characteristic.

17. The system of

Assignees

• Apple Inc

Inventors

• Dibene Ii Joseph T
• Sodhi Inder M
• Cox Keith
• Williams Iii Gerard R

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title