Controlling a guaranteed frequency of a processor

Patent metadata

Field	Value
Publication number	US-2016147275-A1
Application number	US-201414554628-A
Country	US
Kind code	A1
Filing date	Nov 26, 2014
Priority date	Nov 26, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . A processor comprising:
one or more cores to execute instructions; and a power controller coupled to the one or more cores, the power controller including a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the at least one of the one or more cores are to operate for a next window, and to communicate the final guaranteed frequency to at least one entity.

2 . The processor of claim 1 , wherein control logic is to select the final guaranteed frequency to be one of a plurality of requested guaranteed frequencies indicated by the one or more sources.

3 . The processor of claim 2 , wherein the control logic is to select the final guaranteed frequency to be a minimum of the plurality of requested guaranteed frequencies.

4 . The processor of claim 1 , wherein the control logic is to calculate the final guaranteed frequency based at least in part on a power limit to be placed on the processor.

5 . The processor of claim 4 , wherein the control logic is to calculate the final guaranteed frequency further based on a thermal limit to be placed on the processor.

6 . The processor of claim 1 , further comprising a first status register to store a guaranteed frequency change indicator to indicate the dynamic change to the guaranteed frequency.

7 . The processor of claim 6 , further comprising a second status register to store the final guaranteed frequency, wherein responsive to the guaranteed frequency change indicator of the first status register being set, the at least one entity is to read the final guaranteed frequency from the second status register.

8 . The processor of claim 7 , wherein the at least one entity is to reset the guaranteed frequency change indicator of the first status register after the set guaranteed frequency change indicator is read by the at least one entity.

9 . The processor of claim 1 , wherein the control logic is to limit a rate of the dynamic change to the guaranteed frequency.

10 . The processor of claim 9 , wherein the rate comprises a time window during which a second dynamic change to the guaranteed frequency is prevented.

11 . The processor of claim 1 , wherein the control logic is to receive a first guaranteed frequency value associated with a change to a thermal design power value and to receive a second guaranteed frequency value from a graphics engine of the processor, and to determine the final guaranteed frequency to be a lowest one of the first and second guaranteed frequency values.

12 . The processor of claim 1 , wherein the control logic is to receive a third guaranteed frequency value associated with a thermal constraint on the processor and to estimate the final guaranteed frequency based at least in part on the thermal constraint to maintain operation of the processor within the thermal constraint.

13 . The processor of claim 1 , wherein the at least one entity comprises an operating system, and wherein the control logic is to issue an interrupt to the operating system to communicate the dynamic change to the guaranteed frequency to the operating system.

14 . A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
updating a guaranteed frequency value stored in a field of a capabilities register of a processor, the guaranteed frequency value corresponding to a maximum operating frequency at which the processor is guaranteed to operate; setting a change indicator in a field of a status register of the processor to a first state, the change indicator to indicate the update to the guaranteed frequency value; and informing at least one entity of the update to the guaranteed frequency value.

15 . The machine-readable medium of claim 14 , wherein the method further comprises accessing a field of an interrupt register of the processor to determine whether to communicate an interrupt to an operating system to inform the operating system regarding the update to the guaranteed frequency value.

16 . The machine-readable medium of claim 14 , wherein the method further comprises:
receiving a plurality of updated guaranteed frequency values from one or more sources; and determining the updated guaranteed frequency value based at least in part on the plurality of updated guaranteed frequency values.

17 . The machine-readable medium of claim 17 , wherein the method further comprises determining the updated guaranteed frequency value based at least in part on one or more of a power limit or a thermal limit to be placed on the processor.

18 . A system comprising:
a processor including a first domain having a plurality of cores, a second domain having at least one graphics engine, a first set of registers including a capabilities register and a status register, and a power controller including a frequency control logic to dynamically update a guaranteed frequency of the processor to an updated guaranteed frequency, responsive to one or more indications of a guaranteed frequency change received from a plurality of sources, wherein the frequency control logic is to store the updated guaranteed frequency in a first field of the capabilities register and store a change indicator of a first value in a first field of the status register; and a dynamic random access memory (DRAM) coupled to the processor.

19 . The system of claim 18 , wherein an entity is to read the change indicator of the first value in the first field of the first status register and responsive thereto, read the updated guaranteed frequency stored in the first field of the capability register.

20 . The system of claim 18 , wherein the frequency control logic is to prevent the processor from operation at greater than the updated guaranteed frequency during a next time window.

21 . The system of claim 18 , wherein the frequency control logic is to determine the updated guaranteed frequency to be a minimum one of the one or more indications of the guaranteed frequency change.

22 . The system of claim 21 , wherein the frequency control logic is to determine the updated guaranteed frequency value further based at least in part on one or more of a power limit or a thermal limit to be placed on the processor.

Assignees

• Intel Corp

Inventors

• Weissmann Eliezer
• Abu Salah Hisham
• Rotem Efraim
• Therien Guy M
• Shulman Nadav
• Natanzon Esfir
• Diefenbaugh Paul S

Classifications

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/206

  comprising thermal management · CPC title

• G06F1/3228

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title