Display substrate and preparation method therefor, and display apparatus

Patent metadata

Field	Value
Publication number	US-12439783-B2
Application number	US-202117799918-A
Country	US
Kind code	B2
Filing date	Nov 12, 2021
Priority date	Feb 26, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A display substrate and a display device are provided. The display substrate includes a light emitting element disposed on a base substrate, and an encapsulation layer, a connection layer, a light extraction layer, a polarization conversion layer and a polarization layer stacked sequentially at a light exiting side of the light emitting element. The light extraction layer is configured to convert at least a portion of light emitted by the light emitting element incident onto the light extraction layer into circularly polarized light with a set rotational direction to pass through the light extraction layer. The polarization conversion layer is configured to convert the circularly polarized light passing through the light extraction layer into linearly polarized light, with a polarization direction parallel to a direction of a light transmission axis of the polarization layer; the connection layer is configured to bond the light extraction layer to the encapsulation layer.

First claim

The invention claimed is:

1. A display substrate, wherein on a plane perpendicular to the display substrate, the display substrate comprises a base substrate, a buffer layer disposed on the base substrate, a semiconductor layer disposed on the buffer layer, a first insulating layer overlying the semiconductor layer, a first gate metal layer disposed on the first insulating layer, a second insulating layer overlying the first gate metal layer, a second gate metal layer disposed on the second insulating layer, a third insulating layer overlying the second gate metal layer, a first source-drain metal layer disposed on the third insulating layer, and a planarization layer overlying the first source-drain metal layer;
at least one of the first gate metal layer and the second gate metal layer comprises a first power supply line extending in a first direction, and the first source-drain metal layer comprises a data line extending in a second direction, wherein the first direction intersects the second direction.

2. The display substrate according to claim 1 , wherein at least one of the first gate metal layer and the second gate metal layer further comprises a light emitting control signal line and at least one scan signal line, the light emitting control signal line and the at least one scan signal line each extend in the first direction, and the first power supply line is located between the light emitting control signal line and the at least one scan signal line.

3. The display substrate according to claim 1 , wherein the first power supply line comprises at least one first bent part, and the at least one first bent part extends in the second direction.

4. The display substrate according to claim 1 , wherein the first source-drain metal layer further comprises a second power supply line extending in the second direction, and the first power supply line is electrically connected to the second power supply line through a via hole on the third insulating layer, or through via holes on the third insulating layer and the second insulating layer.

5. The display substrate according to claim 1 , wherein the first source-drain metal layer further comprises an eighth connection line extending in the second direction, and an orthographic projection of the eighth connection line on the base substrate intersects an orthographic projection of the first power supply line on the base substrate.

6. The display substrate according to claim 1 , wherein the semiconductor layer comprises a third channel region, a fourth channel region, a fifth channel region, a sixth channel region and a seventh channel region, each of the third channel region, the fourth channel region and the sixth channel region extends in the first direction, the seventh channel region extends in the second direction, the fifth channel region comprises a first sub-channel region and a second sub-channel region which are connected to each other, the first sub-channel region extends in the first direction, and the second sub-channel region extends in the second direction.

7. The display substrate according to claim 1 , wherein the semiconductor layer comprises a reference signal line for supplying a reference voltage signal, and the reference signal line extends in the first direction.

8. The display substrate according to claim 1 , wherein the second gate metal layer comprises an initial signal line for supplying an initial voltage signal; and
the initial signal line comprises at least one third bent part, and the at least one third bent part extends in the second direction.

9. The display substrate according to claim 1 , wherein the display substrate comprises a display area and a mounting area, the mounting area comprises a first pixel circuit, and the display area comprises a second pixel circuit,
wherein each of the first pixel circuit and the second pixel circuit comprises at least one transistor, and the number of transistors in the first pixel circuit is smaller than the number of transistors in the second pixel circuit.

10. The display substrate according to claim 9 , wherein the display substrate further comprises anodes disposed on the planarization layer,
wherein the anodes comprise a first anode and a second anode, the first anode is located in the mounting area, the second anode is located in the display area, and an area of an orthographic projection of the first anode on the base substrate is smaller than an area of an orthographic projection of the second anode on the base substrate.

11. A display apparatus, comprising the display substrate according to claim 1 .

12. A method for preparing a display substrate, comprising:
forming a drive structure layer on a base substrate, wherein the drive structure layer comprises a buffer layer disposed on the base substrate, a semiconductor layer disposed on the buffer layer, a first insulating layer overlying the semiconductor layer, a first gate metal layer disposed on the first insulating layer, a second insulating layer overlying the first gate metal layer, a second gate metal layer disposed on the second insulating layer, a third insulating layer overlying the second gate metal layer, a first source-drain metal layer disposed on the third insulating layer, and a planarization layer overlying the first source-drain metal layer; at least one of the first gate metal layer and the second gate metal layer comprises a first power supply line extending in a first direction, and the first source-drain metal layer comprises a data line extending in a second direction, wherein the first direction intersects the second direction; and
forming a light emitting element on the drive structure layer.

Assignees

• Hefei Boe Joint Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Ding Luke
• Li Yongqian

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• H10K59/124

  Insulating layers formed between TFT elements and OLED elements · CPC title