Display Substrate, Preparation Method thereof, and Display Apparatus

Patent metadata

Field	Value
Publication number	US-2023180521-A1
Application number	US-202017435046-A
Country	US
Kind code	A1
Filing date	Nov 26, 2020
Priority date	Nov 26, 2020
Publication date	Jun 8, 2023
Grant date	—

Abstract

Provided are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a plurality of sub-pixels, and a pixel drive circuit in the sub-pixel includes a drive transistor and a storage capacitor; the display substrate includes a semiconductor layer, a first conductive layer and a second conductive layer which are sequentially disposed on a substrate; the semiconductor layer at least includes an active layer of a drive transistor; the first conductive layer at least includes a first electrode plate; and the second conductive layer at least includes a second electrode plate and an electrode plate connection line, wherein the electrode plate connection line is connected to a second electrode plate in an adjacent sub-pixel in a first direction.

First claim

What is claimed is:

1 . A display substrate, wherein
in a direction parallel to the display substrate, the display substrate comprises a plurality of sub-pixels, at least one sub-pixel comprising a pixel drive circuit and a light emitting device connected to the pixel drive circuit, wherein the pixel drive circuit at least comprises a drive transistor and a storage capacitor; in a direction perpendicular to the display substrate, the display substrate comprises a semiconductor layer, a first conductive layer and a second conductive layer which are sequentially disposed on a substrate; the semiconductor layer at least comprises an active layer of the drive transistor; the first conductive layer at least comprises a first electrode plate of the storage capacitor, and the second conductive layer at least comprises a second electrode plate of the storage capacitor and an electrode plate connection line; the electrode plate connection line is connected to a second electrode plate of an adjacent sub-pixel in a first direction; the first direction is a direction of a sub-pixel row; the active layer of the drive transistor at least comprises a channel region, and the channel region at least comprises a first channel segment extending along the first direction and a second channel segment extending along a second direction, wherein the second direction is a direction of a sub-pixel column; the channel region has a second direction effective length in the second direction, and the second direction effective length is a length of the second channel segment in the second direction; and there is an overlap region between an orthographic projection of the electrode plate connection line on the substrate and an orthographic projection of the semiconductor layer on the substrate, and a distance between the overlap region and the channel region of the drive transistor is greater than or equal to the effective length in the second direction.

2 . The display substrate of claim 1 , wherein the active layer of the drive transistor further comprises a first region and a second region respectively connected to the channel region, and the semiconductor layer in the overlap region comprises a second region of the drive transistor.

3 . The display substrate of claim 2 , wherein the channel region of the drive transistor comprises a first channel segment, a second channel segment, a third channel segment, a fourth channel segment and a fifth channel segment; a first end of the first channel segment is connected to the first region, and a second end of the first channel segment is connected to a first end of the second channel segment after extending along the first direction; a second end of the second channel segment is connected to the first end of the third channel segment after extending along an opposite direction of the second direction; a second end of the third channel segment is connected to a first end of the fourth channel segment after extending along the first direction; a second end of the fourth channel segment is connected to a first end of the fifth channel segment after extending along the second direction; and a second end of the fifth channel segment is connected to the second region after extending along the first direction;
the distance between the overlap region and the channel region of the drive transistor is a distance between an edge of the overlap region adjacent to the fifth channel segment in the second direction and an edge of the fifth channel segment adjacent to the overlap region in the second direction.

4 . The display substrate of claim 1 , wherein the distance between the overlap region and the channel region of the drive transistor is greater than or equal to 1.5 μm.

5 . The display substrate of claim 1 , wherein the distance between the overlap region and the channel region of the drive transistor is 1.6 μm to 4.5 μm.

6 . The display substrate of claim 1 , wherein the pixel drive circuit further comprises a third conductive layer, the third conductive layer at least comprises a first power supply line, and the first power supply line is connected to the second electrode plate through a power via hole; a middle part of the second electrode plate is provided with an opening, and the power via hole is disposed between the opening and the overlap region.

7 . The display substrate of claim 6 , wherein a distance between an edge of the power via hole adjacent to the opening in the first direction and an edge of the opening adjacent to the power via hole in the first direction is greater than or equal to a distance between an edge of the power via hole adjacent to the overlap region in the first direction and an edge of the overlap region adjacent to the power via hole in the first direction.

8 . The display substrate of claim 7 , wherein the distance between an edge of the power via hole adjacent to the opening in the first direction and an edge of the opening adjacent to the power via hole in the first direction is greater than or equal to 0.85 μm.

9 . The display substrate of claim 7 , wherein the distance between an edge of the power via hole adjacent to the opening in the first direction and an edge of the opening adjacent to the power via hole in the first direction is 1.5 μm to 3.0 μm.

10 . The display substrate of claim 7 , wherein the distance between an edge of the power via hole adjacent to the overlap region in the first direction and an edge of the overlap region adjacent to the power via hole in the first direction is greater than or equal to 0.6 μm.

11 . The display substrate of claim 7 , wherein the distance between an edge of the power via hole adjacent to the overlap region in the first direction and an edge of the overlap region adjacent to the power via hole in the first direction is 1.2 μm to 3.0 μm.

12 . The display substrate of claim 2 , wherein conductivity of the second region of the drive transistor is greater than conductivity of the channel region of the drive transistor.

13 . A display apparatus, comprising the display substrate of claim 1 .

14 . A preparation method for a display substrate, wherein in a direction parallel to the display substrate, the display substrate comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel drive circuit and a light emitting device connected to the pixel drive circuit, and the pixel drive circuit at least comprises a drive transistor and a storage capacitor, the method comprising:
sequentially forming a semiconductor layer, a first conductive layer and a second conductive layer on a substrate, wherein the semiconductor layer at least comprises an active layer of the drive transistor; the first conductive layer at least comprises a first electrode plate of the storage capacitor, and the second conductive layer at least comprises a second electrode plate of the storage capacitor and an electrode plate connection line; the electrode plate connection line is connected to a second electrode plate of an adjacent sub-pixel in a first direction; and the first direction is a direction of a sub-pixel row; an active layer of the drive transistor at least comprises a channel region, and the channel region at least comprises a first channel segment extending along the first direction and a second channel segment extending along a second direction, wherein the second direction is a direction of a sub-pixel column; the channel region has a second direction effective length in the second direction, and the second direction effective length is a length of the second channel segment in the second direction; and there is an overlap region between an ort

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Cheng Bo
• Du Mengmeng
• Gou Jie
• Dong Xiangdan
• Ma Hongwei
• Yang Shuangbin
• Li Yujing
• Zhang Zhenhua

Classifications

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/353

  characterised by the geometrical arrangement of the RGB subpixels · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/1213 Primary

  the pixel elements being TFTs · CPC title