Semiconductor device and method for producing semiconductor device

US12439735B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12439735-B2
Application numberUS-202217581256-A
CountryUS
Kind codeB2
Filing dateJan 21, 2022
Priority dateFeb 1, 2021
Publication dateOct 7, 2025
Grant dateOct 7, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

To suppress current leakage between the semiconductor layer below the mask and the buried layer above the mask. To reduce the drive voltage and improve the emission efficiency by improving the efficiency of carrier injection into the active layer. The semiconductor light-emitting device includes a substrate, a mask, a columnar semiconductor, a buried layer, a cathode electrode, and an anode electrode. The substrate has a conductive substrate, an n-type semiconductor layer disposed on the conductive substrate, and a p-type semiconductor layer disposed on the n-type semiconductor layer. The p-type semiconductor layer has a high resistance, thereby enhancing insulation between the n-type semiconductor layer and the buried layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a first n-type semiconductor layer; a tunnel junction layer formed on the first n-type semiconductor layer; a second p-type semiconductor layer formed on the tunnel junction layer; a dielectric mask formed on the second p-type semiconductor layer; a plurality of openings formed on the dielectric mask as holes having a depth reaching the second p-type semiconductor layer; and a plurality of p-type columnar semiconductor formed on the second p-type semiconductor layer of the openings, wherein a mesa is further formed, and the tunnel junction layer and the second p-type semiconductor layer are exposed on a side surface of the mesa, further comprising: a buried layer comprising an n-type semiconductor for filling in a space between the plurality of p-type columnar semiconductors, and wherein the mesa is a trench for separating elements. 2. The semiconductor device according to claim 1 , wherein the columnar semiconductor is exposed on a side surface of the mesa. 3. A semiconductor device comprising: a semiconductor layer of a first type; a tunnel junction layer formed on the semiconductor layer of a first type; a semiconductor layer of a second type formed on the tunnel junction layer; a dielectric mask formed on the semiconductor layer of the second type; a plurality of openings formed on the dielectric mask as holes having a depth reaching the semiconductor layer of the second type; and a plurality of columnar semiconductor of a second type of semiconductor formed on the semiconductor layer of the second type of the openings, wherein a mesa is further formed, and the tunnel junction layer and the semiconductor layer of the second type are exposed on a side surface of the mesa, further comprising: a buried layer comprising a semiconductor of a first type for filling in a space between the plurality of columnar semiconductors of the second type semiconductor, and wherein the mesa is a trench for separating elements. 4. The semiconductor device according to claim 3 , wherein the columnar semiconductor is exposed on a side surface of the mesa. 5. The semiconductor device according to claim 3 , wherein the semiconductor layer of the second type is semiconductor having a conduction type different from a conduction type of the semiconductor layer of the first type. 6. The semiconductor device according to claim 3 , wherein a thickness of the dielectric mask is 2 nm to 50 nm. 7. The semiconductor device according to claim 3 , wherein the semiconductor layer of the second type is undoped semiconductor. 8. The semiconductor device according to claim 3 , wherein the buried layer is semiconductor having a same conduction type as that of the semiconductor layer of the first type.

Assignees

Inventors

Classifications

  • of the light-emitting regions, e.g. non-planar junctions · CPC title

  • within the light-emitting regions, e.g. having quantum confinement structures · CPC title

  • the light-emitting regions comprising nitride materials · CPC title

  • Manufacture or treatment · CPC title

  • the light-emitting regions comprising nitride materials · CPC title

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Frequently asked questions

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What does patent US12439735B2 cover?
To suppress current leakage between the semiconductor layer below the mask and the buried layer above the mask. To reduce the drive voltage and improve the emission efficiency by improving the efficiency of carrier injection into the active layer. The semiconductor light-emitting device includes a substrate, a mask, a columnar semiconductor, a buried layer, a cathode electrode, and an anode ele…
Who is the assignee on this patent?
Toyoda Gosei Kk, Univ Meijo
What technology area does this patent fall under?
Primary CPC classification H10H20/813. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 07 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).