Process technique for embedded memory

Patent metadata

Field	Value
Publication number	US-12439609-B2
Application number	US-202418910873-A
Country	US
Kind code	B2
Filing date	Oct 9, 2024
Priority date	Sep 19, 2023
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A single integrated circuit is provided, comprising a memory region and a non-memory region. The memory region comprises a first conductive structure, a memory element disposed upon the first conductive structure, and a first via disposed upon the memory element. The non-memory region comprises a second conductive structure, and a second via disposed upon the second conductive structure. The first conductive structure and the second conductive structure are formed by a first photolithography process comprising a first photomask, and the first conductive structure is configured to be a first bottom electrode in the memory region. The first via and the second via are formed by a third photolithography process comprising a third photomask. The first photomask and the third photomask comprise a same pattern.

First claim

The invention claimed is:

1. A method for manufacturing an integrated circuit comprising:
defining a memory region and a non-memory region on a semiconductor wafer;
depositing a first interlayer dielectric layer on a first bottom metal layer in the memory region and a second bottom metal layer in the non-memory region;
forming a first conductive structure in the memory region and a second conductive structure in the non-memory region by etching the first interlayer dielectric layer using a first photolithography process comprising a first photomask, wherein the first conductive structure is configured to be a first bottom electrode in the memory region;
depositing a memory stack layer in the memory region and the non-memory region;
forming a memory element in the memory region by etching the memory stack layer using a second photolithography process comprising a second photomask;
depositing a second interlayer dielectric layer in the memory region and the non-memory region; and
forming a first via in the memory region and a second via in the non-memory region by etching the second interlayer dielectric layer using a third photolithography process comprising a third photomask, wherein the first photomask and the third photomask comprise a same pattern.

2. The method of claim 1 , wherein the memory stack layer comprises:
a dielectric layer;
a capping layer; and
a top electrode layer.

3. The method of claim 2 , where the memory stack layer further comprises:
a bottom electrode layer.

4. The method of claim 1 , further comprising:
forming the first bottom metal layer in the memory region and the second bottom metal layer in the non-memory region using a first metallization process.

5. The method of claim 4 , further comprising:
forming a first top metal layer in the memory region and a second top metal layer in the non-memory region using a second metallization process.

Assignees

• Hefei Reliance Memory Ltd

Inventors

• Chen Chao-Yang
• Chang Wen-Hsiung
• Chen Zezhi
• Lu Zhichao

Classifications

• H10N70/20

  Multistable switching devices, e.g. memristors · CPC title

• H10N70/021

  Formation of switching materials, e.g. deposition of layers · CPC title

• H10N70/841

  Electrodes · CPC title

• H10B63/80

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title