Dual-layer dielectric in memory device

Patent metadata

Field	Value
Publication number	US-10134809-B2
Application number	US-201715612245-A
Country	US
Kind code	B2
Filing date	Jun 2, 2017
Priority date	Dec 23, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A system comprising:
a processor; and
a memory coupled to the processor, the memory comprising:
a plurality of wordlines and a plurality of bitlines, individual wordlines of the plurality of wordlines comprising a cell stack having a top electrode layer;
a first dielectric layer disposed between respective pairs of the individual wordlines; and
a second dielectric layer disposed on the first dielectric layer between the respective pairs of the individual wordlines, wherein the plurality of bitlines is disposed on the second dielectric material, wherein the second dielectric layer is formed of a different material than the first dielectric layer, and wherein a lower surface of the second dielectric layer is about at or below a level of a lower surface of the top electrode layer.

2. The system of claim 1 , wherein the first dielectric layer comprises an organic spin-on dielectric material (CSOD), and wherein the second dielectric layer comprises an inorganic dielectric material or alkoxide compound material.

3. The system of claim 1 , wherein the cell stack further comprises a selector device layer and a storage device layer.

4. The system of claim 1 , further comprising a sealing layer coupled to a side surface of the wordlines, wherein a portion of the second dielectric layer is disposed on the sealing layer.

5. The system of claim 1 , wherein the memory further comprises a peripheral portion adjacent to the plurality of wordlines, wherein the peripheral portion comprises:
the first dielectric layer;
the second dielectric layer disposed on the first dielectric material; and
one or more vias disposed through the first and second dielectric layers to provide electrical connectivity for the memory array with circuitry associated with the memory array.

6. The system of claim 1 , wherein the memory comprises a cross-point memory.

7. The system of claim 1 , wherein the system comprises a mobile computing device, the mobile computing device further comprising at least one of:
a display coupled to the processor;
a network interface coupled to the processor; or
a battery coupled to the processor.

Assignees

• Intel Corp

Inventors

• Bernhardt Michael J
• Kim Yudong
• Frost Denzil S
• Allen Tuman Earl
• Baker Kevin Lee
• Yastrebenetsky Kolya
• Weimer Ronald Allen

Classifications

• H10P50/287

  by chemical means · CPC title

• H10W90/725

  between a chip and a laterally-adjacent insulating package substrate, interposer or RDL · CPC title

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/242

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title