Image sensor including time-division controlled correlated double sampler and electronic device including the same

Patent metadata

Field	Value
Publication number	US-12439184-B2
Application number	US-202318329836-A
Country	US
Kind code	B2
Filing date	Jun 6, 2023
Priority date	Jul 15, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

An image sensor includes a pixel array including a first pixel connected to a first column line and a second pixel connected to a second column line, each of the first pixel and the second pixel including a first photodiode (PD) and a second PD, which share a driving transistor, are configured to operate in a first mode and a second mode according to a conversion gain based on the first PD, and are configured to operate in a third mode and a fourth mode based on the second PD; and an analog-to-digital converter including a first correlated double sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit, which read pixel signals output through the first column line and the second column line. The first CDS circuit is connected to the first column line and the second column line in a time-division manner.

First claim

What is claimed is:

1. An image sensor comprising:
a pixel array including a first pixel connected to a first column line and a second pixel connected to a second column line, each of the first pixel and the second pixel including a first photodiode (PD) and a second PD, which share a driving transistor, the first and second pixels configured to operate in a first mode and a second mode according to a conversion gain based on the respective first PD, and the first and second pixels configured to operate in a third mode and a fourth mode based on the respective second PD; and
an analog-to-digital converter including a first correlated double sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit, which are configured to read pixel signals output through the first column line and the second column line,
wherein the first CDS circuit is configured to connect to the first column line and the second column line in a time-division manner,
wherein the first CDS circuit is configured to read, in a first period, a first mode pixel signal of the first pixel that is output through the first column line, and is configured to read, in a second period after the first period, a first mode pixel signal of the second pixel that is output through the second column line, and
wherein the second CDS circuit is configured to read, in the first period, a second mode pixel signal of the first pixel that is output through the first column line, and is configured to read, in the second period, a second mode pixel signal of the second pixel that is output through the second column line.

2. The image sensor of claim 1 , wherein
the first mode pixel signal includes a reset level and a signal level, and
the first CDS circuit is configured to read the signal level after reading the reset level.

3. The image sensor of claim 1 , wherein the first period includes a first sub-period, a second sub-period, a third sub-period, and a fourth sub-period, the first CDS circuit is configured to read a reset level of the first mode pixel signal in the first sub-period, the second CDS circuit is configured to read a reset level of the second mode pixel signal in the second sub-period, the second CDS circuit is configured to read a signal level of the second mode pixel signal in the third sub-period, the first CDS circuit is configured to read a signal level of the first mode pixel signal in the fourth sub-period, and a first conversion gain of the first mode is less than a second conversion gain of the second mode.

4. The image sensor of claim 1 , wherein the third CDS circuit is configured to read, in the second period, a third mode pixel signal of the first pixel and a fourth mode pixel signal of the first pixel, output through the first column line.

5. The image sensor of claim 1 , wherein layout areas of at least one of the first CDS circuit, the second CDS circuit, and the third CDS circuit is different from at least one other of the first CDS circuit, the second CDS circuit, and the third CDS circuit.

6. The image sensor of claim 1 , wherein a first light-receiving area of the first PD is greater than a second light-receiving area of the second PD.

7. The image sensor of claim 1 , wherein each of the first pixel and the second pixel further includes:
a first transfer transistor connected to the first PD and to a first floating diffusion node (FD);
a gain control transistor connected to the first FD and to a second FD;
a reset transistor connected to the second FD and having one end configured to receive a first power supply voltage;
a second transfer transistor connected to the second PD and to a third FD;
a switching transistor connected to the second FD and to the third FD; and
a capacitor connected to the third FD and having one end configured to receive the first power supply voltage.

8. The image sensor of claim 7 , wherein the capacitor is configured to store charges overflowing from the second PD.

9. The image sensor of claim 7 , wherein,
in the first mode, the gain control transistor is configured to turn on and the switching transistor and the reset transistor are configured to turn off,
in the second mode, the gain control transistor, the switching transistor, and the reset transistor are configured to turn off,
in the third mode, the gain control transistor and the switching transistor are configured to turn on and the reset transistor is configured to turn off, and
in the fourth mode, the control transistor and the switching transistor are configured to turn on and the reset transistor is configured to toggle once.

10. The image sensor of claim 1 , wherein the first pixel and the second pixel are in a same column and adjacent rows.

11. The image sensor of claim 1 , wherein the first pixel and the second pixel are in adjacent columns and a same row.

12. An image sensor comprising:
a pixel array including a plurality of pixels, a plurality of row lines configured to provide control signals to the plurality of pixels, and a plurality of column lines configured to output a plurality of pixel signals generated from the plurality of pixels, each of the plurality of pixels including a first photodiode (PD) and a second PD sharing a driving transistor;
an analog-to-digital converter configured to convert a plurality of pixel signals output through the column lines, the analog-to-digital converter including a first correlated double sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit, which are configured to read pixel signals received through a first column line and through a second column line that are among the plurality of column lines; and
a switching circuit configured to time-divisionally connect the first column line to the first CDS circuit and the second CDS circuit and connect the second column line to the third CDS circuit in a first period, and to time-divisionally connect the second column line to the first CDS circuit and the second CDS circuit and connect the first column line to the third CDS circuit in a second period.

13. The image sensor of claim 12 , wherein each of the plurality of pixels are configured to operate in a first mode and a second mode according to a conversion gain based on the first PD and to operate in a third mode and a fourth mode according to an output order of a reset level and a signal level based on the second PD.

14. The image sensor of claim 13 , wherein,
in the first period, the first CDS circuit is configured to read a first mode signal of a first pixel received through the first column line, the second CDS circuit is configured to read a second mode signal of the first pixel received through the first column line, the third CDS circuit is configured to read a third mode signal and a fourth mode signal of a second pixel received through the second column line; and
in the second period, the first CDS circuit is configured to read a first mode signal of a third pixel received through the second column line, the second CDS circuit is configured to read a second mode signal of the third pixel received through the second column line, and the third CDS circuit is configured to read a third mode signal and a fourth mode signal of the first pixel received through the first column line.

15. The image sensor of claim 12 , wherein the first CDS circuit and the second CDS circuit are on a first side of the pixel array, the third CDS circuit is on a second side of the pixel array, and the first side and the second side are sides perpendicular to a direction in which the first column line and the second column line extend.

16. An electronic device c

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Seokyong
• Kim Kyungmin
• Kim Donghyun

Classifications

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H04N25/585

  with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes · CPC title

• H04N25/616

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H04N25/78 Primary

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title