Phase-locked loop update cancellation

Patent metadata

Field	Value
Publication number	US-12438547-B2
Application number	US-202318492453-A
Country	US
Kind code	B2
Filing date	Oct 23, 2023
Priority date	Oct 23, 2023
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A pulse limiter circuit of a phase-locked loop (PLL) receives, from a phase frequency detector of the PLL, first second input pulses, where pulse widths of the first and second input pulses indicate whether a reference clock signal leads or lags a feedback clock signal. The pulse limiter circuit determines whether a pulse width of the first or second input pulse is greater than a selected duration indicative of transient phase jitter. Based on determining the pulse width of the first or second input pulse is greater than the selected duration, the pulse limiter circuit sets a pulse width of a first output pulse equal to a pulse width of a second output pulse width and outputs the first and second output pulses to a charge pump of the PLL, such that no phase adjustment to the feedback clock signal is made based on the first and second input pulses.

First claim

What is claimed is:

1. A phase-locked loop pulse cancelation method, the method comprising:
receiving, from a phase frequency detector of a phase-locked loop (PLL) at a pulse limiter circuit of the PLL, a first input pulse and a second input pulse, wherein pulse widths of the first and second input pulses indicate whether a reference clock signal of the PLL leads or lags a feedback clock signal of the PLL;
delaying the first and second input pulses by the selected duration to obtain a delayed first input pulse and a delayed second input pulse;
determining, by the pulse limiter circuit, whether a pulse width of the first input pulse or a pulse width of the second input pulse is greater than a selected duration by logically ANDing the first input pulse with the delayed first input pulse and logically ANDing the second input pulse with the delayed second input pulse;
based on determining the pulse width of the first input pulse or the pulse width of the second input pulse is greater than the selected duration:
setting, by the pulse limiter circuit, a pulse width of a first output pulse equal to a pulse width of a second output pulse width; and
sending, by the pulse limiter circuit, the first and second output pulses to a charge pump of the PLL, such that no phase adjustment to the feedback clock signal is made based on the first and second input pulses.

2. The method of claim 1 , further comprising:
selecting, by the pulse limiter circuit, the selected duration based on a select signal.

3. The method of claim 1 , wherein:
the setting comprises performing the setting based on assertion of an enable signal; and
the method further comprises based on the enable signal being deasserted, sending, by the pulse limiter circuit to the charge pump, first and second output pulses having the pulse widths of the first and second input pulses, respectively.

4. The method of claim 1 , wherein the setting includes:
latching, by a latch of the pulse limiter circuit, a signal indicative of determining the pulse width of the first input pulse is greater than the selected duration; and
outputting from the latch an override signal that sets the pulse width of the second output pulse.

5. A phase-locked loop comprising:
a phase frequency detector;
a pulse limiter coupled to the phase frequency detector;
a charge pump coupled to the pulse limiter; and
a voltage-controlled oscillator (VCO) coupled to the charge pump;
wherein the pulse limiter is configured to:
receive, from the phase frequency detector, a first input pulse and a second input pulse, wherein pulse widths of the first and second input pulses indicate whether a reference clock signal of the PLL leads or lags a feedback clock signal of the PLL;
delay the first input pulse and the second input pulse by a selectable duration to obtain a delayed first input pulse and a delayed second input pulse;
determine whether a pulse width of the first input pulse or a pulse width of the second input pulse is greater than a selected duration by logically ANDing the first input pulse with the delayed first input pulse and logically ANDing the second input pulse with the delayed second input pulse;
based on determining the pulse width of the first input pulse or the pulse width of the second input pulse is greater than the selected duration:
set a pulse width of a first output pulse equal to a pulse width of a second output pulse width; and
send the first and second output pulses to the charge pump, such that no phase adjustment to the feedback clock signal is made by the VCO based on the first and second input pulses.

6. The phase-locked loop of claim 5 , wherein the pulse limiter is further configured to select the selected duration based on a select signal.

7. The phase-locked loop of claim 5 , wherein:
the setting comprises performing the setting based on assertion of an enable signal; and the pulse limiter is further configured to, based on the enable signal being deasserted,
send to the charge pump first and second output pulses having the pulse widths of the first and second input pulses, respectively.

8. The phase-locked loop of claim 5 , wherein the setting includes:
latching, by a latch, a signal indicative of determining the pulse width of the first input pulse is greater than the selected duration; and
outputting from the latch an override signal that sets the pulse width of the second output pulse.

9. A phase-locked loop comprising:
a phase frequency detector configured to receive a reference clock signal and a feedback clock signal and to output first and second input pulses, wherein pulse widths of the first and second input pulses indicate whether the reference clock signal leads or lags the feedback clock signal;
a pulse limiter including:
first and second detection circuits coupled to receive the first input pulse and the second input pulse, respectively, wherein the first and second detection circuits are configured to detect whether a pulse width of the first input pulse or a pulse width of the second input pulse is greater than a selected duration indicative of transient phase jitter and to generate respective first and second detect signals;
first and second latch circuits configured to set based on assertion of the first and second detect signals, respectively, and to reset based on assertion of a delayed first input pulse and a delayed second input pulse, respectively; and
a first output circuit coupled to receive as inputs an output of the second latch and the delayed first input pulse and a second output circuit coupled to receive as inputs an output of the first latch and the delayed second input pulse, wherein the first and second output circuits are configured to respectively output first and second output pulses based on their inputs in lieu of the first and second input pulses of the phase frequency detector.

10. The phase-locked loop of claim 9 , wherein the first detection circuit comprises:
a delay circuit that generates the delayed first input pulse based on the first input pulse; and
an AND gate that logically combines the first input pulse and the delayed first input pulse.

11. The phase-locked loop of claim 9 , wherein:
the first detection circuit comprises a delay circuit that generates the delayed first input pulse based on the first input pulse; and
the delay circuit is configured to impose a delay of selectable duration based on an a select signal.

12. The phase-locked loop of claim 9 , wherein each of the first and second output circuits comprises an OR gate.

13. The phase-locked loop of claim 9 , further comprising:
a charge pump coupled to received the first and second output pules; and
a voltage-controlled oscillator (VCO) controlled by the charge pump, wherein the VCO generates the feedback clock signal.

14. The phase-locked loop of claim 9 , wherein the first detection circuit is configured to enable and disable output of the first detect signal based on an enable signal.

Assignees

• IBM

Inventors

• Borkenhagen John
• Steffen Christopher
• Kesselring Grant P
• Strom James

Classifications

• H03L7/0891 Primary

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title